piso.vhd

来自「Bcode_s_m_h.rar实现GPSB码接收、译码等工程」· VHDL 代码 · 共 63 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity piso is
port(data_in :in std_logic_vector(19 downto 0);
     clk :in std_logic;
     clk_in:in std_logic;
     j_in :in std_logic;
     data_out:out std_logic;
     data_clk_out:out std_logic);
end piso;
architecture a of piso is
  signal m:std_logic:='0';
  signal w:std_logic:='0';
  signal q:std_logic_vector(19 downto 0);
  signal n:integer range 0 to 20;
begin
process(m,j_in,clk)
begin
 if(clk'event and clk='1')then
  if(j_in='1')then
    q<=data_in;
    w<='1';
    n<=1;
  elsif(m='1')then
    q<=(others=>'0');
    n<=0; 
    w<='0';
  else
      n<=n+1;
      data_out<=q(19);
    for i in 1 to 19 loop
      q(i)<=q(i-1);  
    end loop;     
  end if;
  end if;
end process;
process(clk,n)
begin
  if(clk'event and clk='1')then
    if(n=20)then
      m<='1';
    else
      m<='0';
    end if;
   end if;
end process;

process(clk,w,n)
begin
  if(w='1'and n>=2)then
  data_clk_out<=clk_in;
  elsif(w='0')then
  data_clk_out<='0';
  elsif(w='1'and n=1)then
  data_clk_out<='0';
  else
  null;
  end if;
end process;
end a;