📄 translator_shift.rpt
字号:
80 - - - 23 OUTPUT 0 1 0 0 quit_out22
83 - - - 13 OUTPUT 0 1 0 0 quit_out23
29 - - C -- OUTPUT 0 1 0 0 quit_out24
28 - - C -- OUTPUT 0 1 0 0 quit_out25
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\bcode_s_m_h\translator_shift.rpt
translator_shift
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 18 AND2 0 2 0 1 |LPM_ADD_SUB:2981|addcore:adder|:63
- 5 - A 18 AND2 0 3 0 2 |LPM_ADD_SUB:2981|addcore:adder|:67
- 1 - A 21 AND2 0 2 0 1 |LPM_ADD_SUB:2981|addcore:adder|:71
- 3 - C 13 DFFE + 0 2 1 0 :5
- 5 - C 13 DFFE + 0 2 1 0 :7
- 7 - C 13 DFFE + 0 2 1 0 :9
- 3 - C 24 DFFE + 0 2 1 0 :11
- 6 - C 24 DFFE + 0 2 1 0 :13
- 2 - C 24 DFFE + 0 2 1 0 :15
- 4 - C 24 DFFE + 0 2 1 0 :17
- 1 - C 17 DFFE + 0 2 1 0 :19
- 4 - C 17 DFFE + 0 2 1 0 :21
- 1 - C 21 DFFE + 0 2 1 0 :23
- 5 - C 17 DFFE + 0 2 1 0 :25
- 3 - A 17 DFFE + 0 2 1 0 :27
- 8 - A 18 DFFE + 0 2 1 0 :29
- 1 - A 16 DFFE + 0 2 1 0 :31
- 8 - A 13 DFFE + 0 2 1 0 :33
- 3 - A 13 DFFE + 0 2 1 0 :35
- 1 - A 13 DFFE + 0 2 1 0 :37
- 4 - A 13 DFFE + 0 2 1 0 :39
- 3 - B 20 DFFE + 0 2 1 0 :41
- 5 - B 20 DFFE + 0 2 1 0 :43
- 1 - B 20 DFFE + 0 2 1 0 :45
- 2 - B 20 DFFE + 0 2 1 0 :47
- 5 - B 13 DFFE + 0 2 1 0 :49
- 1 - B 13 DFFE + 0 2 1 0 :51
- 4 - B 13 DFFE + 0 2 1 0 :53
- 7 - B 13 DFFE + 0 2 1 0 :55
- 7 - A 21 DFFE + 0 3 1 0 :60
- 3 - A 21 DFFE + 0 3 0 1 x4 (:66)
- 4 - A 21 DFFE + 0 3 0 2 x3 (:67)
- 2 - A 18 DFFE + 0 3 0 2 x2 (:68)
- 4 - A 18 DFFE + 0 3 0 3 x1 (:69)
- 3 - A 18 DFFE + 0 2 0 5 x0 (:70)
- 8 - C 13 DFFE + 1 2 0 2 q_out25 (:71)
- 6 - C 13 DFFE + 0 3 0 2 q_out24 (:72)
- 1 - C 13 DFFE + 0 3 0 2 q_out23 (:73)
- 8 - C 24 DFFE + 0 3 0 2 q_out22 (:74)
- 7 - C 24 DFFE + 0 3 0 2 q_out21 (:75)
- 5 - C 24 DFFE + 0 3 0 2 q_out20 (:76)
- 1 - C 24 DFFE + 0 3 0 2 q_out19 (:77)
- 7 - C 17 DFFE + 0 3 0 2 q_out18 (:78)
- 6 - C 17 DFFE + 0 3 0 2 q_out17 (:79)
- 8 - C 17 DFFE + 0 3 0 2 q_out16 (:80)
- 3 - C 17 DFFE + 0 3 0 2 q_out15 (:81)
- 2 - C 17 DFFE + 0 3 0 2 q_out14 (:82)
- 7 - A 18 DFFE + 0 3 0 2 q_out13 (:83)
- 1 - A 18 DFFE + 0 3 0 2 q_out12 (:84)
- 7 - A 13 DFFE + 0 3 0 2 q_out11 (:85)
- 5 - A 13 DFFE + 0 3 0 2 q_out10 (:86)
- 2 - A 13 DFFE + 0 3 0 2 q_out9 (:87)
- 6 - A 13 DFFE + 0 3 0 2 q_out8 (:88)
- 8 - B 20 DFFE + 0 3 0 2 q_out7 (:89)
- 7 - B 20 DFFE + 0 3 0 2 q_out6 (:90)
- 6 - B 20 DFFE + 0 3 0 2 q_out5 (:91)
- 4 - B 20 DFFE + 0 3 0 2 q_out4 (:92)
- 8 - B 13 DFFE + 0 3 0 2 q_out3 (:93)
- 6 - B 13 DFFE + 0 3 0 2 q_out2 (:94)
- 3 - B 13 DFFE + 0 3 0 2 q_out1 (:95)
- 2 - B 13 DFFE + 0 3 0 1 q_out0 (:96)
- 6 - A 21 OR2 2 0 0 2 :146
- 2 - A 21 OR2 2 0 0 31 :155
- 2 - C 13 AND2 ! 0 1 0 30 :203
- 4 - C 13 OR2 s 3 0 0 2 ~205~1
- 8 - A 21 AND2 s ! 0 4 0 2 ~6319~1
- 5 - A 21 OR2 s 0 3 0 26 ~6725~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\bcode_s_m_h\translator_shift.rpt
translator_shift
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 0/ 48( 0%) 14/ 48( 29%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
B: 4/ 96( 4%) 0/ 48( 0%) 9/ 48( 18%) 0/16( 0%) 8/16( 50%) 0/16( 0%)
C: 6/ 96( 6%) 0/ 48( 0%) 10/ 48( 20%) 1/16( 6%) 8/16( 50%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\bcode_s_m_h\translator_shift.rpt
translator_shift
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 58 clk
Device-Specific Information: e:\bcode_s_m_h\translator_shift.rpt
translator_shift
** EQUATIONS **
clk : INPUT;
clr : INPUT;
in_data0 : INPUT;
in_data1 : INPUT;
in_data2 : INPUT;
in_data3 : INPUT;
j_in : INPUT;
-- Node name is 'j_out'
-- Equation name is 'j_out', type is output
j_out = _LC7_A21;
-- Node name is ':96' = 'q_out0'
-- Equation name is 'q_out0', location is LC2_B13, type is buried.
q_out0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC2_A21 & _LC2_C13 & q_out1
# !_LC2_A21 & q_out0
# !_LC2_C13 & q_out0;
-- Node name is ':95' = 'q_out1'
-- Equation name is 'q_out1', location is LC3_B13, type is buried.
q_out1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !_LC2_A21 & q_out1
# !_LC2_C13 & q_out1
# _LC2_A21 & _LC2_C13 & q_out2;
-- Node name is ':94' = 'q_out2'
-- Equation name is 'q_out2', location is LC6_B13, type is buried.
q_out2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC2_A21 & q_out2
# !_LC2_C13 & q_out2
# _LC2_A21 & _LC2_C13 & q_out3;
-- Node name is ':93' = 'q_out3'
-- Equation name is 'q_out3', location is LC8_B13, type is buried.
q_out3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !_LC2_A21 & q_out3
# !_LC2_C13 & q_out3
# _LC2_A21 & _LC2_C13 & q_out4;
-- Node name is ':92' = 'q_out4'
-- Equation name is 'q_out4', location is LC4_B20, type is buried.
q_out4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC2_A21 & q_out4
# !_LC2_C13 & q_out4
# _LC2_A21 & _LC2_C13 & q_out5;
-- Node name is ':91' = 'q_out5'
-- Equation name is 'q_out5', location is LC6_B20, type is buried.
q_out5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC2_A21 & q_out5
# !_LC2_C13 & q_out5
# _LC2_A21 & _LC2_C13 & q_out6;
-- Node name is ':90' = 'q_out6'
-- Equation name is 'q_out6', location is LC7_B20, type is buried.
q_out6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC2_A21 & q_out6
# !_LC2_C13 & q_out6
# _LC2_A21 & _LC2_C13 & q_out7;
-- Node name is ':89' = 'q_out7'
-- Equation name is 'q_out7', location is LC8_B20, type is buried.
q_out7 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !_LC2_A21 & q_out7
# !_LC2_C13 & q_out7
# _LC2_A21 & _LC2_C13 & q_out8;
-- Node name is ':88' = 'q_out8'
-- Equation name is 'q_out8', location is LC6_A13, type is buried.
q_out8 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !_LC2_A21 & q_out8
# !_LC2_C13 & q_out8
# _LC2_A21 & _LC2_C13 & q_out9;
-- Node name is ':87' = 'q_out9'
-- Equation name is 'q_out9', location is LC2_A13, type is buried.
q_out9 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !_LC2_A21 & q_out9
# !_LC2_C13 & q_out9
# _LC2_A21 & _LC2_C13 & q_out10;
-- Node name is ':86' = 'q_out10'
-- Equation name is 'q_out10', location is LC5_A13, type is buried.
q_out10 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ011 = !_LC2_A21 & q_out10
# !_LC2_C13 & q_out10
# _LC2_A21 & _LC2_C13 & q_out11;
-- Node name is ':85' = 'q_out11'
-- Equation name is 'q_out11', location is LC7_A13, type is buried.
q_out11 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = !_LC2_A21 & q_out11
# !_LC2_C13 & q_out11
# _LC2_A21 & _LC2_C13 & q_out12;
-- Node name is ':84' = 'q_out12'
-- Equation name is 'q_out12', location is LC1_A18, type is buried.
q_out12 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, VCC);
_EQ013 = !_LC2_A21 & q_out12
# !_LC2_C13 & q_out12
# _LC2_A21 & _LC2_C13 & q_out13;
-- Node name is ':83' = 'q_out13'
-- Equation name is 'q_out13', location is LC7_A18, type is buried.
q_out13 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, VCC);
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