📄 translator_shift.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity translator_shift is
port(in_data:in std_logic_vector(3 downto 0);
quit_out:out std_logic_vector(25 downto 0);
clr,clk,j_in:in std_logic;
j_out:out std_logic);
end translator_shift;
architecture a of translator_shift is
signal q_out: std_logic_vector(25 downto 0);
signal m:std_logic:='0';
signal w:std_logic:='0';
signal x:integer range 0 to 26;
signal p:std_logic_vector(1 downto 0);
begin
process(clr,in_data)
begin
if(clr='1')then
m<='0';
w<='0';
elsif(j_in='1')then
m<='1';
w<='1';
else
null;
end if;
if(in_data="0111")then
p<="11";
elsif(in_data="0011")then
p<="10";
else
p<="00";
end if;
end process;
process(clk,p)
begin
if(clk'event and clk='1')then
if(w='0')then
x<=0;
elsif(p(1)='1')then
x<=x+1;
q_out(25)<=p(0);
for i in 25 downto 1 loop
q_out(i-1)<=q_out(i);
end loop;
end if;
end if;
end process;
process(clk,m,in_data)
begin
if(clk'event and clk='1')then
if(m='0')then
j_out<='0';
elsif(x=26)then
quit_out<=q_out(25 downto 0);
j_out<='1';
else
null;
end if;
end if;
end process;
end a;
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