📄 bcode_s_m_h.rpt
字号:
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\bcode_s_m_h\bcode_s_m_h.rpt
bcode_s_m_h
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
73 - - A -- OUTPUT 0 1 0 0 serial_data
59 - - C -- OUTPUT 0 1 0 0 serial_data_clk
7 - - - 03 OUTPUT 0 1 0 0 times0
28 - - C -- OUTPUT 0 1 0 0 times1
27 - - C -- OUTPUT 0 1 0 0 times2
37 - - - 09 OUTPUT 0 1 0 0 times3
38 - - - 10 OUTPUT 0 1 0 0 times4
62 - - C -- OUTPUT 0 1 0 0 times5
29 - - C -- OUTPUT 0 1 0 0 times6
30 - - C -- OUTPUT 0 1 0 0 times7
61 - - C -- OUTPUT 0 1 0 0 times8
58 - - C -- OUTPUT 0 1 0 0 times9
60 - - C -- OUTPUT 0 1 0 0 times10
16 - - A -- OUTPUT 0 1 0 0 times11
17 - - A -- OUTPUT 0 1 0 0 times12
19 - - A -- OUTPUT 0 1 0 0 times13
70 - - A -- OUTPUT 0 1 0 0 times14
69 - - A -- OUTPUT 0 1 0 0 times15
72 - - A -- OUTPUT 0 1 0 0 times16
18 - - A -- OUTPUT 0 1 0 0 times17
71 - - A -- OUTPUT 0 1 0 0 times18
80 - - - 23 OUTPUT 0 1 0 0 times19
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\bcode_s_m_h\bcode_s_m_h.rpt
bcode_s_m_h
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 3 - A 19 AND2 0 2 0 3 |COUNTER_TIME:1|LPM_ADD_SUB:85|addcore:adder|:67
- 8 - A 19 AND2 0 3 0 2 |COUNTER_TIME:1|LPM_ADD_SUB:85|addcore:adder|:75
- 5 - A 19 DFFE + 1 2 0 2 |COUNTER_TIME:1|n5 (|COUNTER_TIME:1|:8)
- 2 - A 19 DFFE + 1 1 0 3 |COUNTER_TIME:1|n4 (|COUNTER_TIME:1|:9)
- 7 - A 19 DFFE + 1 2 0 2 |COUNTER_TIME:1|n3 (|COUNTER_TIME:1|:10)
- 4 - A 19 DFFE + 1 1 0 3 |COUNTER_TIME:1|n2 (|COUNTER_TIME:1|:11)
- 6 - A 14 DFFE + 1 1 0 5 |COUNTER_TIME:1|n1 (|COUNTER_TIME:1|:12)
- 6 - A 19 DFFE + 1 0 0 4 |COUNTER_TIME:1|n0 (|COUNTER_TIME:1|:13)
- 2 - A 14 OR2 s ! 0 2 0 3 |COUNTER_TIME:1|~279~1
- 1 - A 14 AND2 0 4 0 2 |COUNTER_TIME:1|:279
- 7 - A 04 AND2 0 2 0 1 |DETECT:2|LPM_ADD_SUB:104|addcore:adder|:67
- 6 - A 04 AND2 0 3 0 1 |DETECT:2|LPM_ADD_SUB:104|addcore:adder|:71
- 4 - A 04 AND2 0 4 0 2 |DETECT:2|LPM_ADD_SUB:104|addcore:adder|:75
- 5 - A 10 AND2 0 2 0 1 |DETECT:2|LPM_ADD_SUB:104|addcore:adder|:79
- 5 - A 02 DFFE + 0 3 0 4 |DETECT:2|current_state1 (|DETECT:2|:12)
- 8 - A 02 DFFE + 0 4 0 4 |DETECT:2|current_state0 (|DETECT:2|:13)
- 6 - A 10 DFFE + 0 3 0 1 |DETECT:2|c5 (|DETECT:2|:16)
- 4 - A 10 DFFE + 0 3 0 2 |DETECT:2|c4 (|DETECT:2|:17)
- 8 - A 04 DFFE + 0 3 0 3 |DETECT:2|c3 (|DETECT:2|:18)
- 5 - A 04 DFFE + 0 3 0 4 |DETECT:2|c2 (|DETECT:2|:19)
- 1 - A 04 DFFE + 0 3 0 5 |DETECT:2|c1 (|DETECT:2|:20)
- 3 - A 04 DFFE + 0 2 0 6 |DETECT:2|c0 (|DETECT:2|:21)
- 3 - A 02 AND2 0 2 0 7 |DETECT:2|:128
- 2 - A 04 AND2 0 4 0 1 |DETECT:2|:312
- 1 - A 10 OR2 s 0 2 0 2 |DETECT:2|~351~1
- 6 - A 02 OR2 s 0 3 0 1 |DETECT:2|~351~2
- 4 - A 02 OR2 ! 0 4 0 2 |DETECT:2|:456
- 7 - A 02 OR2 0 4 0 1 |DETECT:2|:475
- 1 - A 02 OR2 0 2 0 2 |DETECT:2|:582
- 3 - A 23 DFFE + 0 2 1 1 |HOURS_OUT:19|:27
- 4 - A 13 DFFE + 0 2 1 1 |HOURS_OUT:19|:29
- 5 - A 23 DFFE + 0 2 1 1 |HOURS_OUT:19|:31
- 2 - A 16 DFFE + 0 2 1 1 |HOURS_OUT:19|:33
- 8 - A 16 DFFE + 0 2 1 1 |HOURS_OUT:19|:35
- 5 - A 21 DFFE + 0 2 1 1 |HOURS_OUT:19|:37
- 7 - A 11 DFFE + 0 2 1 1 |MINUTES_OUT:18|:27
- 2 - A 22 DFFE + 0 2 1 1 |MINUTES_OUT:18|:29
- 1 - A 22 DFFE + 0 2 1 1 |MINUTES_OUT:18|:31
- 4 - C 13 DFFE + 0 2 1 1 |MINUTES_OUT:18|:33
- 7 - C 20 DFFE + 0 2 1 1 |MINUTES_OUT:18|:35
- 2 - C 20 DFFE + 0 2 1 1 |MINUTES_OUT:18|:37
- 6 - C 08 DFFE + 0 2 1 1 |MINUTES_OUT:18|:39
- 3 - C 19 AND2 0 3 0 2 |PISO:21|LPM_ADD_SUB:1842|addcore:adder|:67
- 1 - A 23 DFFE + 0 3 1 0 |PISO:21|:24
- 8 - A 23 DFFE + 0 4 0 1 |PISO:21|q19 (|PISO:21|:27)
- 7 - A 23 DFFE + 0 4 0 1 |PISO:21|q18 (|PISO:21|:28)
- 6 - A 23 DFFE + 0 4 0 1 |PISO:21|q17 (|PISO:21|:29)
- 1 - A 16 DFFE + 0 4 0 1 |PISO:21|q16 (|PISO:21|:30)
- 7 - A 16 DFFE + 0 4 0 1 |PISO:21|q15 (|PISO:21|:31)
- 6 - A 16 DFFE + 0 4 0 1 |PISO:21|q14 (|PISO:21|:32)
- 5 - A 16 DFFE + 0 4 0 1 |PISO:21|q13 (|PISO:21|:33)
- 4 - A 16 DFFE + 0 4 0 1 |PISO:21|q12 (|PISO:21|:34)
- 2 - C 13 DFFE + 0 4 0 1 |PISO:21|q11 (|PISO:21|:35)
- 3 - C 13 DFFE + 0 4 0 1 |PISO:21|q10 (|PISO:21|:36)
- 1 - C 20 DFFE + 0 4 0 1 |PISO:21|q9 (|PISO:21|:37)
- 8 - C 20 DFFE + 0 4 0 1 |PISO:21|q8 (|PISO:21|:38)
- 3 - C 08 DFFE + 0 4 0 1 |PISO:21|q7 (|PISO:21|:39)
- 8 - C 08 DFFE + 0 4 0 1 |PISO:21|q6 (|PISO:21|:40)
- 7 - C 08 DFFE + 0 4 0 1 |PISO:21|q5 (|PISO:21|:41)
- 5 - C 08 DFFE + 0 4 0 1 |PISO:21|q4 (|PISO:21|:42)
- 1 - C 10 DFFE + 0 4 0 1 |PISO:21|q3 (|PISO:21|:43)
- 7 - C 10 DFFE + 0 4 0 1 |PISO:21|q2 (|PISO:21|:44)
- 5 - C 10 DFFE + 0 4 0 1 |PISO:21|q1 (|PISO:21|:45)
- 1 - C 04 DFFE + 0 3 0 1 |PISO:21|q0 (|PISO:21|:46)
- 1 - C 23 DFFE + 0 2 0 1 |PISO:21|w (|PISO:21|:47)
- 7 - C 19 DFFE + 0 3 0 3 |PISO:21|n4 (|PISO:21|:48)
- 5 - C 19 DFFE + 0 3 0 2 |PISO:21|n3 (|PISO:21|:49)
- 8 - C 19 DFFE + 0 3 0 4 |PISO:21|n2 (|PISO:21|:50)
- 2 - C 08 DFFE + 0 3 0 3 |PISO:21|n1 (|PISO:21|:51)
- 2 - A 23 DFFE + 0 2 0 5 |PISO:21|n0 (|PISO:21|:52)
- 1 - C 19 DFFE + 0 4 0 25 |PISO:21|m (|PISO:21|:53)
- 1 - C 08 AND2 s 0 2 0 3 |PISO:21|~3673~1
- 6 - C 19 AND2 s 0 2 0 3 |PISO:21|~4021~1
- 5 - C 23 OR2 0 3 1 0 |PISO:21|:4087
- 4 - C 19 OR2 s 1 3 0 1 |PISO:21|~4088~1
- 2 - C 19 AND2 s 0 4 0 1 |PISO:21|~4089~1
- 5 - C 11 DFFE + 0 2 1 1 |SECONDS_OUT:20|:27
- 1 - C 11 DFFE + 0 2 1 1 |SECONDS_OUT:20|:29
- 3 - A 10 DFFE + 0 2 1 1 |SECONDS_OUT:20|:31
- 6 - C 10 DFFE + 0 2 1 1 |SECONDS_OUT:20|:33
- 1 - C 09 DFFE + 0 2 1 1 |SECONDS_OUT:20|:35
- 3 - C 09 DFFE + 0 2 1 1 |SECONDS_OUT:20|:37
- 4 - C 04 DFFE + 0 2 1 1 |SECONDS_OUT:20|:39
- 6 - A 08 AND2 0 2 0 1 |TRANSLATOR_SHIFT:3|LPM_ADD_SUB:2981|addcore:adder|:63
- 2 - A 08 AND2 0 3 0 2 |TRANSLATOR_SHIFT:3|LPM_ADD_SUB:2981|addcore:adder|:67
- 4 - A 08 AND2 0 2 0 1 |TRANSLATOR_SHIFT:3|LPM_ADD_SUB:2981|addcore:adder|:71
- 7 - A 13 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:9
- 8 - A 13 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:11
- 4 - A 23 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:15
- 3 - A 16 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:17
- 2 - A 21 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:19
- 8 - A 21 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:21
- 4 - A 11 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:25
- 8 - A 22 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:27
- 7 - A 22 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:29
- 1 - C 13 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:33
- 6 - C 20 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:35
- 4 - C 20 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:37
- 4 - C 08 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:39
- 8 - C 11 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:41
- 7 - C 11 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:43
- 7 - A 10 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:45
- 4 - C 10 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:49
- 8 - C 09 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:51
- 7 - C 09 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:53
- 4 - C 09 DFFE + 0 2 0 1 |TRANSLATOR_SHIFT:3|:55
- 2 - A 10 SOFT s ! 0 1 0 6 |TRANSLATOR_SHIFT:3|~60~1
- 3 - A 11 DFFE + 0 3 0 51 |TRANSLATOR_SHIFT:3|:60
- 5 - A 08 DFFE + 0 3 0 1 |TRANSLATOR_SHIFT:3|x4 (|TRANSLATOR_SHIFT:3|:66)
- 3 - A 08 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|x3 (|TRANSLATOR_SHIFT:3|:67)
- 7 - A 08 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|x2 (|TRANSLATOR_SHIFT:3|:68)
- 8 - A 08 DFFE + 0 3 0 3 |TRANSLATOR_SHIFT:3|x1 (|TRANSLATOR_SHIFT:3|:69)
- 1 - A 11 DFFE + 0 2 0 5 |TRANSLATOR_SHIFT:3|x0 (|TRANSLATOR_SHIFT:3|:70)
- 3 - A 14 DFFE + 0 3 0 1 |TRANSLATOR_SHIFT:3|q_out25 (|TRANSLATOR_SHIFT:3|:71)
- 2 - A 13 DFFE + 0 3 0 1 |TRANSLATOR_SHIFT:3|q_out24 (|TRANSLATOR_SHIFT:3|:72)
- 6 - A 13 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out23 (|TRANSLATOR_SHIFT:3|:73)
- 5 - A 13 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out22 (|TRANSLATOR_SHIFT:3|:74)
- 1 - A 13 DFFE + 0 3 0 1 |TRANSLATOR_SHIFT:3|q_out21 (|TRANSLATOR_SHIFT:3|:75)
- 3 - A 13 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out20 (|TRANSLATOR_SHIFT:3|:76)
- 7 - A 21 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out19 (|TRANSLATOR_SHIFT:3|:77)
- 6 - A 21 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out18 (|TRANSLATOR_SHIFT:3|:78)
- 4 - A 21 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out17 (|TRANSLATOR_SHIFT:3|:79)
- 3 - A 21 DFFE + 0 3 0 1 |TRANSLATOR_SHIFT:3|q_out16 (|TRANSLATOR_SHIFT:3|:80)
- 1 - A 21 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out15 (|TRANSLATOR_SHIFT:3|:81)
- 6 - A 22 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out14 (|TRANSLATOR_SHIFT:3|:82)
- 5 - A 22 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out13 (|TRANSLATOR_SHIFT:3|:83)
- 4 - A 22 DFFE + 0 3 0 1 |TRANSLATOR_SHIFT:3|q_out12 (|TRANSLATOR_SHIFT:3|:84)
- 3 - A 22 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out11 (|TRANSLATOR_SHIFT:3|:85)
- 3 - C 20 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out10 (|TRANSLATOR_SHIFT:3|:86)
- 5 - C 20 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out9 (|TRANSLATOR_SHIFT:3|:87)
- 3 - C 11 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out8 (|TRANSLATOR_SHIFT:3|:88)
- 6 - C 11 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out7 (|TRANSLATOR_SHIFT:3|:89)
- 4 - C 11 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out6 (|TRANSLATOR_SHIFT:3|:90)
- 2 - C 11 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out5 (|TRANSLATOR_SHIFT:3|:91)
- 3 - C 10 DFFE + 0 3 0 1 |TRANSLATOR_SHIFT:3|q_out4 (|TRANSLATOR_SHIFT:3|:92)
- 2 - C 10 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out3 (|TRANSLATOR_SHIFT:3|:93)
- 6 - C 09 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out2 (|TRANSLATOR_SHIFT:3|:94)
- 5 - C 09 DFFE + 0 3 0 2 |TRANSLATOR_SHIFT:3|q_out1 (|TRANSLATOR_SHIFT:3|:95)
- 2 - C 09 DFFE + 0 3 0 1 |TRANSLATOR_SHIFT:3|q_out0 (|TRANSLATOR_SHIFT:3|:96)
- 2 - A 11 OR2 0 2 0 2 |TRANSLATOR_SHIFT:3|:146
- 8 - A 11 OR2 0 2 0 31 |TRANSLATOR_SHIFT:3|:155
- 2 - A 02 AND2 s 0 4 0 3 |TRANSLATOR_SHIFT:3|~162~1
- 5 - A 14 AND2 0 4 0 2 |TRANSLATOR_SHIFT:3|:162
- 7 - A 14 OR2 ! 0 4 0 30 |TRANSLATOR_SHIFT:3|:203
- 1 - A 19 AND2 s ! 1 2 0 2 |TRANSLATOR_SHIFT:3|~205~1
- 4 - A 14 OR2 ! 0 3 0 1 |TRANSLATOR_SHIFT:3|:205
- 1 - A 08 OR2 s 0 4 0 2 |TRANSLATOR_SHIFT:3|~6319~1
- 5 - A 11 OR2 s 0 3 0 20 |TRANSLATOR_SHIFT:3|~6572~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\bcode_s_m_h\bcode_s_m_h.rpt
bcode_s_m_h
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 15/ 96( 15%) 15/ 48( 31%) 18/ 48( 37%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 15/ 96( 15%) 11/ 48( 22%) 8/ 48( 16%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 3/24( 12%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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