piso.rpt

Bcode_s_m_h.rar实现GPSB码接收、译码等工程

-- Node name is ':42' = 'q4' 
-- Equation name is 'q4', location is LC7_A16, type is buried.
q4       = DFFE( _EQ011, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ011 = !j_in & !m &  q3
         #  data_in4 &  j_in;

-- Node name is ':41' = 'q5' 
-- Equation name is 'q5', location is LC8_A16, type is buried.
q5       = DFFE( _EQ012, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ012 = !j_in & !m &  q4
         #  data_in5 &  j_in;

-- Node name is ':40' = 'q6' 
-- Equation name is 'q6', location is LC4_A16, type is buried.
q6       = DFFE( _EQ013, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ013 = !j_in & !m &  q5
         #  data_in6 &  j_in;

-- Node name is ':39' = 'q7' 
-- Equation name is 'q7', location is LC1_C18, type is buried.
q7       = DFFE( _EQ014, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ014 = !j_in & !m &  q6
         #  data_in7 &  j_in;

-- Node name is ':38' = 'q8' 
-- Equation name is 'q8', location is LC3_C18, type is buried.
q8       = DFFE( _EQ015, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ015 = !j_in & !m &  q7
         #  data_in8 &  j_in;

-- Node name is ':37' = 'q9' 
-- Equation name is 'q9', location is LC4_C18, type is buried.
q9       = DFFE( _EQ016, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ016 = !j_in & !m &  q8
         #  data_in9 &  j_in;

-- Node name is ':36' = 'q10' 
-- Equation name is 'q10', location is LC5_C18, type is buried.
q10      = DFFE( _EQ017, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ017 = !j_in & !m &  q9
         #  data_in10 &  j_in;

-- Node name is ':35' = 'q11' 
-- Equation name is 'q11', location is LC6_C18, type is buried.
q11      = DFFE( _EQ018, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ018 = !j_in & !m &  q10
         #  data_in11 &  j_in;

-- Node name is ':34' = 'q12' 
-- Equation name is 'q12', location is LC7_C18, type is buried.
q12      = DFFE( _EQ019, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ019 = !j_in & !m &  q11
         #  data_in12 &  j_in;

-- Node name is ':33' = 'q13' 
-- Equation name is 'q13', location is LC8_C18, type is buried.
q13      = DFFE( _EQ020, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ020 = !j_in & !m &  q12
         #  data_in13 &  j_in;

-- Node name is ':32' = 'q14' 
-- Equation name is 'q14', location is LC2_C18, type is buried.
q14      = DFFE( _EQ021, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ021 = !j_in & !m &  q13
         #  data_in14 &  j_in;

-- Node name is ':31' = 'q15' 
-- Equation name is 'q15', location is LC1_C23, type is buried.
q15      = DFFE( _EQ022, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ022 = !j_in & !m &  q14
         #  data_in15 &  j_in;

-- Node name is ':30' = 'q16' 
-- Equation name is 'q16', location is LC4_C23, type is buried.
q16      = DFFE( _EQ023, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ023 = !j_in & !m &  q15
         #  data_in16 &  j_in;

-- Node name is ':29' = 'q17' 
-- Equation name is 'q17', location is LC6_A23, type is buried.
q17      = DFFE( _EQ024, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ024 = !j_in & !m &  q16
         #  data_in17 &  j_in;

-- Node name is ':28' = 'q18' 
-- Equation name is 'q18', location is LC7_A23, type is buried.
q18      = DFFE( _EQ025, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ025 = !j_in & !m &  q17
         #  data_in18 &  j_in;

-- Node name is ':27' = 'q19' 
-- Equation name is 'q19', location is LC8_A23, type is buried.
q19      = DFFE( _EQ026, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ026 = !j_in & !m &  q18
         #  data_in19 &  j_in;

-- Node name is ':47' = 'w' 
-- Equation name is 'w', location is LC3_A23, type is buried.
w        = DFFE( _EQ027, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ027 = !m &  w
         #  j_in;

-- Node name is '|LPM_ADD_SUB:1842|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_A13', type is buried 
_LC6_A13 = LCELL( _EQ028);
  _EQ028 =  n0 &  n1 &  n2;

-- Node name is ':24' 
-- Equation name is '_LC1_A23', type is buried 
_LC1_A23 = DFFE( _EQ029, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ029 =  j_in &  _LC1_A23
         #  _LC1_A23 &  m
         # !j_in & !m &  q19;

-- Node name is '~3673~1' 
-- Equation name is '~3673~1', location is LC1_A16, type is buried.
-- synthesized logic cell 
_LC1_A16 = LCELL( _EQ030);
  _EQ030 = !j_in & !m;

-- Node name is '~4021~1' 
-- Equation name is '~4021~1', location is LC3_A13, type is buried.
-- synthesized logic cell 
_LC3_A13 = LCELL( _EQ031);
  _EQ031 = !n1 & !n3;

-- Node name is ':4087' 
-- Equation name is '_LC5_A23', type is buried 
_LC5_A23 = LCELL( _EQ032);
  _EQ032 =  _LC2_A13 &  _LC5_A23 &  w
         #  _LC4_A23 &  w;

-- Node name is '~4088~1' 
-- Equation name is '~4088~1', location is LC4_A23, type is buried.
-- synthesized logic cell 
_LC4_A23 = LCELL( _EQ033);
  _EQ033 =  clk_in &  n2
         #  clk_in &  n4
         #  clk_in & !_LC3_A13;

-- Node name is '~4089~1' 
-- Equation name is '~4089~1', location is LC2_A13, type is buried.
-- synthesized logic cell 
_LC2_A13 = LCELL( _EQ034);
  _EQ034 =  _LC3_A13 & !n0 & !n2 & !n4;



Project Information                                    e:\bcode_s_m_h\piso.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 20,623K