📄 piso.rpt
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/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\bcode_s_m_h\piso.rpt
piso
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
70 - - A -- OUTPUT 0 1 0 0 data_clk_out
73 - - A -- OUTPUT 0 1 0 0 data_out
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\bcode_s_m_h\piso.rpt
piso
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - A 13 AND2 0 3 0 2 |LPM_ADD_SUB:1842|addcore:adder|:67
- 1 - A 23 DFFE + 1 2 1 0 :24
- 8 - A 23 DFFE + 2 2 0 1 q19 (:27)
- 7 - A 23 DFFE + 2 2 0 1 q18 (:28)
- 6 - A 23 DFFE + 2 2 0 1 q17 (:29)
- 4 - C 23 DFFE + 2 2 0 1 q16 (:30)
- 1 - C 23 DFFE + 2 2 0 1 q15 (:31)
- 2 - C 18 DFFE + 2 2 0 1 q14 (:32)
- 8 - C 18 DFFE + 2 2 0 1 q13 (:33)
- 7 - C 18 DFFE + 2 2 0 1 q12 (:34)
- 6 - C 18 DFFE + 2 2 0 1 q11 (:35)
- 5 - C 18 DFFE + 2 2 0 1 q10 (:36)
- 4 - C 18 DFFE + 2 2 0 1 q9 (:37)
- 3 - C 18 DFFE + 2 2 0 1 q8 (:38)
- 1 - C 18 DFFE + 2 2 0 1 q7 (:39)
- 4 - A 16 DFFE + 2 2 0 1 q6 (:40)
- 8 - A 16 DFFE + 2 2 0 1 q5 (:41)
- 7 - A 16 DFFE + 2 2 0 1 q4 (:42)
- 6 - A 16 DFFE + 2 2 0 1 q3 (:43)
- 5 - A 16 DFFE + 2 2 0 1 q2 (:44)
- 3 - A 16 DFFE + 2 2 0 1 q1 (:45)
- 2 - A 16 DFFE + 2 1 0 1 q0 (:46)
- 3 - A 23 DFFE + 1 1 0 1 w (:47)
- 5 - A 13 DFFE + 0 3 0 3 n4 (:48)
- 7 - A 13 DFFE + 1 2 0 2 n3 (:49)
- 4 - A 13 DFFE + 0 3 0 4 n2 (:50)
- 8 - A 13 DFFE + 1 2 0 3 n1 (:51)
- 2 - A 23 DFFE + 1 1 0 5 n0 (:52)
- 1 - A 13 DFFE + 0 4 0 25 m (:53)
- 1 - A 16 AND2 s 1 1 0 3 ~3673~1
- 3 - A 13 AND2 s 0 2 0 3 ~4021~1
- 5 - A 23 OR2 0 3 1 0 :4087
- 4 - A 23 OR2 s 1 3 0 1 ~4088~1
- 2 - A 13 AND2 s 0 4 0 1 ~4089~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\bcode_s_m_h\piso.rpt
piso
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 8/ 96( 8%) 0/ 48( 0%) 10/ 48( 20%) 7/16( 43%) 2/16( 12%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 9/ 96( 9%) 0/ 48( 0%) 4/ 48( 8%) 9/16( 56%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\bcode_s_m_h\piso.rpt
piso
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 28 clk
Device-Specific Information: e:\bcode_s_m_h\piso.rpt
piso
** EQUATIONS **
clk : INPUT;
clk_in : INPUT;
data_in0 : INPUT;
data_in1 : INPUT;
data_in2 : INPUT;
data_in3 : INPUT;
data_in4 : INPUT;
data_in5 : INPUT;
data_in6 : INPUT;
data_in7 : INPUT;
data_in8 : INPUT;
data_in9 : INPUT;
data_in10 : INPUT;
data_in11 : INPUT;
data_in12 : INPUT;
data_in13 : INPUT;
data_in14 : INPUT;
data_in15 : INPUT;
data_in16 : INPUT;
data_in17 : INPUT;
data_in18 : INPUT;
data_in19 : INPUT;
j_in : INPUT;
-- Node name is 'data_clk_out'
-- Equation name is 'data_clk_out', type is output
data_clk_out = _LC5_A23;
-- Node name is 'data_out'
-- Equation name is 'data_out', type is output
data_out = _LC1_A23;
-- Node name is ':53' = 'm'
-- Equation name is 'm', location is LC1_A13, type is buried.
m = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC3_A13 & !n0 & n2 & n4;
-- Node name is ':52' = 'n0'
-- Equation name is 'n0', location is LC2_A23, type is buried.
n0 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = j_in
# !m & !n0;
-- Node name is ':51' = 'n1'
-- Equation name is 'n1', location is LC8_A13, type is buried.
n1 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !j_in & !m & n0 & !n1
# !j_in & !m & !n0 & n1;
-- Node name is ':50' = 'n2'
-- Equation name is 'n2', location is LC4_A13, type is buried.
n2 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_A16 & !n0 & n2
# _LC1_A16 & !n1 & n2
# _LC1_A16 & n0 & n1 & !n2;
-- Node name is ':49' = 'n3'
-- Equation name is 'n3', location is LC7_A13, type is buried.
n3 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !j_in & !_LC6_A13 & !m & n3
# !j_in & _LC6_A13 & !m & !n3;
-- Node name is ':48' = 'n4'
-- Equation name is 'n4', location is LC5_A13, type is buried.
n4 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC1_A16 & !n3 & n4
# _LC1_A16 & !_LC6_A13 & n4
# _LC1_A16 & _LC6_A13 & n3 & !n4;
-- Node name is ':46' = 'q0'
-- Equation name is 'q0', location is LC2_A16, type is buried.
q0 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC1_A16 & q0
# data_in0 & j_in;
-- Node name is ':45' = 'q1'
-- Equation name is 'q1', location is LC3_A16, type is buried.
q1 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !j_in & !m & q0
# data_in1 & j_in;
-- Node name is ':44' = 'q2'
-- Equation name is 'q2', location is LC5_A16, type is buried.
q2 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = !j_in & !m & q1
# data_in2 & j_in;
-- Node name is ':43' = 'q3'
-- Equation name is 'q3', location is LC6_A16, type is buried.
q3 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = !j_in & !m & q2
# data_in3 & j_in;
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