detect.vhd

Bcode_s_m_h.rar实现GPSB码接收、译码等工程

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ENTITY detect IS
   PORT( 
      clk      : IN     std_logic;
      clr      : IN     std_logic;
      j_out    : OUT    std_logic;
      in_data  : IN     std_logic_vector (3 DOWNTO 0);
      out_data : OUT    std_logic_vector (3 DOWNTO 0)
   );

-- Declarations

END detect ;


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;


ARCHITECTURE fsm OF detect IS

   -- Architecture Declarations
   signal c:integer range 0 to 60;

   TYPE STATE_TYPE IS (
      s0,
      s1,
      s2
   );

   -- State vector declaration
   ATTRIBUTE state_vector : string;
   ATTRIBUTE state_vector OF fsm : ARCHITECTURE IS "current_state" ;


   -- Declare current and next state signals
   SIGNAL current_state : STATE_TYPE ;
   SIGNAL next_state : STATE_TYPE ;

BEGIN

   ----------------------------------------------------------------------------
   clocked : PROCESS(
      clk,
      clr
   )
   ----------------------------------------------------------------------------
   BEGIN
      IF (clr = '1') THEN
         current_state <= s0;
         -- Reset Values
      ELSIF (clk'EVENT AND clk = '1') THEN
         current_state <= next_state;
         -- Default Assignment To Internals
         c <= 0;

         -- Combined Actions for internal signals only
         CASE current_state IS
         WHEN s0 =>
            c<=0;
         WHEN s1 =>
            c<=c+1;
         WHEN OTHERS =>
            NULL;
         END CASE;
                                                                  
      END IF;

   END PROCESS clocked;

   ----------------------------------------------------------------------------
   nextstate : PROCESS (
      c,
      clr,
      current_state,
      in_data
   )
   ----------------------------------------------------------------------------
   BEGIN
      CASE current_state IS
      WHEN s0 =>
         IF (in_data="1111") THEN
            next_state <= s1;
         ELSE
            next_state <= s0;
         END IF;
      WHEN s1 =>
         IF (c>=49 and in_data="1111") THEN
            next_state <= s2;
         ELSIF (c>60) THEN
            next_state <= s0;
         ELSE
            next_state <= s1;
         END IF;
      WHEN s2 =>
         IF (clr='1') THEN
            next_state <= s0;
         ELSE
            next_state <= s2;
         END IF;
      WHEN OTHERS =>
         next_state <= s0;
      END CASE;

   END PROCESS nextstate;

   ----------------------------------------------------------------------------
   output : PROCESS (
      current_state,
      in_data
   )
   ----------------------------------------------------------------------------
   BEGIN
      -- Default Assignment
      out_data <= "0000";
      -- Default Assignment To Internals

      -- Combined Actions
      CASE current_state IS
      WHEN s0 =>
         out_data<="0000";
         j_out<='0';
      WHEN s2 =>
         out_data<=in_data;
         j_out<='1';
      WHEN OTHERS =>
         NULL;
      END CASE;

   END PROCESS output;

   -- Concurrent Statements

END fsm;