📄 minutes_out.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity minutes_out is
port(quit_in:in std_logic_vector(25 downto 0);
qa:out std_logic_vector(2 downto 0);
qb:out std_logic_vector(3 downto 0);
clk,j_in:in std_logic);
end minutes_out;
architecture a of minutes_out is
begin
process(clk,j_in)
begin
if(clk'event and clk='1')then
if(j_in='1')then
qa<=quit_in(15 downto 13);
qb<=quit_in(11 downto 8);
else
null;
end if;
end if;
end process;
end a;
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