📄 detect.rpt
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Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\bcode_s_m_h\detect.rpt
detect
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: e:\bcode_s_m_h\detect.rpt
detect
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 3 clr
Device-Specific Information: e:\bcode_s_m_h\detect.rpt
detect
** EQUATIONS **
clk : INPUT;
clr : INPUT;
in_data0 : INPUT;
in_data1 : INPUT;
in_data2 : INPUT;
in_data3 : INPUT;
-- Node name is 'clr~1'
-- Equation name is 'clr~1', location is LC1_B1, type is buried.
-- synthesized logic cell
!_LC1_B1 = _LC1_B1~NOT;
_LC1_B1~NOT = LCELL(!clr);
-- Node name is ':13' = 'current_state0'
-- Equation name is 'current_state0', location is LC4_B6, type is buried.
current_state0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = _LC8_B6
# !current_state0 & !current_state1 & _LC1_B7;
-- Node name is ':12' = 'current_state1'
-- Equation name is 'current_state1', location is LC3_B6, type is buried.
current_state1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = current_state1 & _LC7_B6
# current_state0 & _LC7_B6;
-- Node name is ':21' = 'c0'
-- Equation name is 'c0', location is LC2_B12, type is buried.
c0 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, !_LC1_B1);
_EQ003 = !c0 & _LC2_B6;
-- Node name is ':20' = 'c1'
-- Equation name is 'c1', location is LC6_B12, type is buried.
c1 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, !_LC1_B1);
_EQ004 = c0 & !c1 & _LC2_B6
# !c0 & c1 & _LC2_B6;
-- Node name is ':19' = 'c2'
-- Equation name is 'c2', location is LC7_B12, type is buried.
c2 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, !_LC1_B1);
_EQ005 = c2 & _LC2_B6 & !_LC8_B12
# !c2 & _LC2_B6 & _LC8_B12;
-- Node name is ':18' = 'c3'
-- Equation name is 'c3', location is LC3_B12, type is buried.
c3 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, !_LC1_B1);
_EQ006 = c3 & _LC2_B6 & !_LC5_B12
# !c3 & _LC2_B6 & _LC5_B12;
-- Node name is ':17' = 'c4'
-- Equation name is 'c4', location is LC3_B7, type is buried.
c4 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, !_LC1_B1);
_EQ007 = c4 & !_LC1_B12 & _LC2_B6
# !c4 & _LC1_B12 & _LC2_B6;
-- Node name is ':16' = 'c5'
-- Equation name is 'c5', location is LC4_B12, type is buried.
c5 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, !_LC1_B1);
_EQ008 = c5 & _LC2_B6 & !_LC7_B7
# !c5 & _LC2_B6 & _LC7_B7;
-- Node name is 'j_out'
-- Equation name is 'j_out', type is output
j_out = _LC1_B6;
-- Node name is 'out_data0'
-- Equation name is 'out_data0', type is output
out_data0 = _LC4_B7;
-- Node name is 'out_data1'
-- Equation name is 'out_data1', type is output
out_data1 = _LC6_B7;
-- Node name is 'out_data2'
-- Equation name is 'out_data2', type is output
out_data2 = _LC8_B7;
-- Node name is 'out_data3'
-- Equation name is 'out_data3', type is output
out_data3 = _LC2_B7;
-- Node name is '|LPM_ADD_SUB:104|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B12', type is buried
_LC8_B12 = LCELL( _EQ009);
_EQ009 = c0 & c1;
-- Node name is '|LPM_ADD_SUB:104|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B12', type is buried
_LC5_B12 = LCELL( _EQ010);
_EQ010 = c0 & c1 & c2;
-- Node name is '|LPM_ADD_SUB:104|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B12', type is buried
_LC1_B12 = LCELL( _EQ011);
_EQ011 = c0 & c1 & c2 & c3;
-- Node name is '|LPM_ADD_SUB:104|addcore:adder|:79' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B7', type is buried
_LC7_B7 = LCELL( _EQ012);
_EQ012 = c4 & _LC1_B12;
-- Node name is ':128'
-- Equation name is '_LC2_B6', type is buried
_LC2_B6 = LCELL( _EQ013);
_EQ013 = current_state0 & !current_state1;
-- Node name is ':312'
-- Equation name is '_LC6_B6', type is buried
_LC6_B6 = LCELL( _EQ014);
_EQ014 = !c0 & !c1 & !c2 & !c3;
-- Node name is '~342~1'
-- Equation name is '~342~1', location is LC1_B7, type is buried.
-- synthesized logic cell
_LC1_B7 = LCELL( _EQ015);
_EQ015 = in_data0 & in_data1 & in_data2 & in_data3;
-- Node name is '~351~1'
-- Equation name is '~351~1', location is LC5_B7, type is buried.
-- synthesized logic cell
_LC5_B7 = LCELL( _EQ016);
_EQ016 = !c4
# !c5;
-- Node name is '~351~2'
-- Equation name is '~351~2', location is LC5_B6, type is buried.
-- synthesized logic cell
_LC5_B6 = LCELL( _EQ017);
_EQ017 = _LC5_B7
# !c0 & !c1;
-- Node name is ':456'
-- Equation name is '_LC7_B6', type is buried
!_LC7_B6 = _LC7_B6~NOT;
_LC7_B6~NOT = LCELL( _EQ018);
_EQ018 = _LC2_B6 & _LC6_B6
# !_LC1_B7 & _LC2_B6
# _LC2_B6 & _LC5_B7;
-- Node name is ':475'
-- Equation name is '_LC8_B6', type is buried
_LC8_B6 = LCELL( _EQ019);
_EQ019 = _LC5_B6 & !_LC7_B6
# !c3 & !_LC7_B6
# !c2 & !_LC7_B6;
-- Node name is ':548'
-- Equation name is '_LC2_B7', type is buried
_LC2_B7 = LCELL( _EQ020);
_EQ020 = !current_state0 & current_state1 & in_data3;
-- Node name is ':557'
-- Equation name is '_LC8_B7', type is buried
_LC8_B7 = LCELL( _EQ021);
_EQ021 = !current_state0 & current_state1 & in_data2;
-- Node name is ':566'
-- Equation name is '_LC6_B7', type is buried
_LC6_B7 = LCELL( _EQ022);
_EQ022 = !current_state0 & current_state1 & in_data1;
-- Node name is ':575'
-- Equation name is '_LC4_B7', type is buried
_LC4_B7 = LCELL( _EQ023);
_EQ023 = !current_state0 & current_state1 & in_data0;
-- Node name is ':582'
-- Equation name is '_LC1_B6', type is buried
_LC1_B6 = LCELL( _EQ024);
_EQ024 = !current_state0 & current_state1
# current_state1 & _LC1_B6
# current_state0 & _LC1_B6;
Project Information e:\bcode_s_m_h\detect.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 29,172K
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