📄 pci_wbs_wbb3_2_wbb2.v
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<tr><td><font size=-2> </font></td></tr> </table></td><td width=10><img width=10 src="/images/dotty.gif"></td><td background="/images/vpd.gif"><img width=1 src="/images/dotty.gif"></td><td width=10><img width=10 src="/images/dotty.gif"></td><td valign=top> <table width=100% cellpadding=2 cellspacing=0 border=0> <tr><td><img height=2 src="/images/dotty.gif"></td></tr> </table> <table width=100% cellspacing=0 cellpadding=0 border=0><tr><td><!-- pf_body_start --> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html><head><title>pci/rtl/verilog/pci_wbs_wbb3_2_wbb2.v - view - 1.5</title><meta name="robots" content="nofollow" /><meta name="generator" content="FreeBSD-CVSweb 3.0.5" /><meta http-equiv="Content-Script-Type" content="text/javascript" /><meta http-equiv="Content-Style-Type" content="text/css" /><link rel="stylesheet" type="text/css" href="/css/cvsweb.css" /></head><body class="src"><table class="navigate-header" width="100%" summary="Navigation"> <tr> <td><a href="./pci_wbs_wbb3_2_wbb2.v#rev1.5"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_wbs_wbb3_2_wbb2.v#rev1.5">pci_wbs_wbb3_2_wbb2.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td> <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td> </tr></table><hr /><div class="log-markup">File: <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_wbs_wbb3_2_wbb2.v">pci_wbs_wbb3_2_wbb2.v</a><br /><a name="rev1.5"></a><a name="HEAD"></a> Revision <b>1.5</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_wbs_wbb3_2_wbb2.v?rev=1.5;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_wbs_wbb3_2_wbb2.v?rev=1.5;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_wbs_wbb3_2_wbb2.v?annotate=1.5">annotated</a> - <a href="pci_wbs_wbb3_2_wbb2.v?r1=1.5#rev1.5">select for diffs</a><br /><i>Mon Aug 16 09:12:01 2004 UTC</i> (2 years, 9 months ago) by <i>mihad</i><br />Branches: <a href="./pci_wbs_wbb3_2_wbb2.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_wbs_wbb3_2_wbb2.v?only_with_tag=HEAD">HEAD</a><br /><pre class="log">Removed unsinthesizable !== comparation.</pre></div><hr /><pre>////////////////////////////////////////////////////////////////////////// //////// File name "pci_wbs_wbb3_2_wbb2.v" //////// //////// This file is part of the "PCI bridge" project //////// http://www.opencores.org/cores/pci/ //////// //////// Author(s): //////// - Miha Dolenc (mihad@opencores.org) //////// //////// //////// ////////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: pci_wbs_wbb3_2_wbb2.v,v $// Revision 1.5 2004/08/16 09:12:01 mihad// Removed unsinthesizable !== comparation.//// Revision 1.4 2004/01/24 11:54:18 mihad// Update! SPOCI Implemented!//// Revision 1.3 2003/12/19 11:11:30 mihad// Compact PCI Hot Swap support added.// New testcases added.// Specification updated.// Test application changed to support WB B3 cycles.//// Revision 1.2 2003/12/01 16:20:56 simons// ifdef - endif statements put in separate lines for flint compatibility.//// Revision 1.1 2003/08/12 13:58:19 mihad// Module that converts slave WISHBONE B3 accesses to// WISHBONE B2 accesses with CAB.////module pci_wbs_wbb3_2_wbb2( wb_clk_i, wb_rst_i, wbs_cyc_i, wbs_cyc_o, wbs_stb_i, wbs_stb_o, wbs_adr_i, wbs_adr_o, wbs_dat_i_i, wbs_dat_i_o, wbs_dat_o_i, wbs_dat_o_o, wbs_we_i, wbs_we_o, wbs_sel_i, wbs_sel_o, wbs_ack_i, wbs_ack_o, wbs_err_i, wbs_err_o, wbs_rty_i, wbs_rty_o, wbs_cti_i, wbs_bte_i, wbs_cab_o, wb_init_complete_i) ;input wb_clk_i ;input wb_rst_i ;input wbs_cyc_i ;output wbs_cyc_o ;input wbs_stb_i ;output wbs_stb_o ;input [31:0] wbs_adr_i ;output [31:0] wbs_adr_o ;input [31:0] wbs_dat_i_i ;output [31:0] wbs_dat_i_o ;input [31:0] wbs_dat_o_i ;output [31:0] wbs_dat_o_o ;input wbs_we_i ;output wbs_we_o ;input [ 3:0] wbs_sel_i ;output [ 3:0] wbs_sel_o ;input wbs_ack_i ;output wbs_ack_o ;input wbs_err_i ;output wbs_err_o ;input wbs_rty_i ;output wbs_rty_o ;input [ 2:0] wbs_cti_i ;input [ 1:0] wbs_bte_i ;output wbs_cab_o ;input wb_init_complete_i ;reg wbs_cyc_o ;reg [31:0] wbs_adr_o ;reg [31:0] wbs_dat_i_o ;reg wbs_dat_i_o_valid ;reg [31:0] wbs_dat_o_o ;reg wbs_we_o ;reg [ 3:0] wbs_sel_o ;reg wbs_ack_o ;reg wbs_err_o ;reg wbs_rty_o ; reg wbs_cab_o ;always@(posedge wb_rst_i or posedge wb_clk_i)begin if (wb_rst_i) begin wbs_cyc_o <= 1'b0 ; wbs_adr_o <= 32'h0 ; wbs_dat_i_o <= 32'h0 ; wbs_dat_o_o <= 32'h0 ; wbs_sel_o <= 4'h0 ; wbs_we_o <= 1'b0 ; wbs_dat_i_o_valid <= 1'b0 ; wbs_cab_o <= 1'b0 ; end else begin:transfer_and_transfer_adr_ctrl_blk reg start_cycle ; reg [3:0] end_cycle ; reg generate_int_adr ; start_cycle = ~wbs_cyc_o & wbs_cyc_i & wbs_stb_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o & wb_init_complete_i ; // there is a few conditions when cycle must be terminated // I've put them into bit array for better readability of the code // 1st condition - pci bridge is signaling an error end_cycle[0] = wbs_err_i ; // 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines end_cycle[1] = wbs_rty_i `ifdef PCI_WBS_B3_RTY_DISABLE & 1'b0 `endif ; // 3rd condition - end non burst cycles as soon as pci bridge response is received end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ; // 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ; if (wbs_dat_i_o_valid) begin if (wbs_ack_i | wbs_err_i `ifdef PCI_WBS_B3_RTY_DISABLE `else | wbs_rty_i `endif ) wbs_dat_i_o_valid <= 1'b0 ; end else begin if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o & wb_init_complete_i) begin wbs_dat_i_o <= wbs_dat_i_i ; wbs_dat_i_o_valid <= 1'b1 ; end end if (start_cycle) begin wbs_cyc_o <= 1'b1 ; wbs_sel_o <= wbs_sel_i ; wbs_we_o <= wbs_we_i ; if (wbs_cti_i == 3'b010) begin case (wbs_bte_i) 2'b00: begin wbs_cab_o <= 1'b1 ; end 2'b01: begin if (wbs_adr_i[3:2] == 2'b00) wbs_cab_o <= 1'b1 ; else wbs_cab_o <= 1'b0 ; end 2'b10: begin if (wbs_adr_i[4:2] == 3'b000) wbs_cab_o <= 1'b1 ; else wbs_cab_o <= 1'b0 ; end 2'b11: begin if (wbs_adr_i[5:2] == 4'b0000) wbs_cab_o <= 1'b1 ; else wbs_cab_o <= 1'b0 ; end endcase end else begin wbs_cab_o <= 1'b0 ; end end else if ( wbs_cyc_o & (|end_cycle) ) begin wbs_cyc_o <= 1'b0 ; end if (start_cycle) wbs_adr_o <= wbs_adr_i ; else if (wbs_ack_i) wbs_adr_o[31:2] <= wbs_adr_o[31:2] + 1'b1 ; if (~wbs_we_o & wbs_ack_i) wbs_dat_o_o <= wbs_dat_o_i ; endendalways@(posedge wb_rst_i or posedge wb_clk_i)begin if (wb_rst_i) begin wbs_ack_o <= 1'b0 ; wbs_err_o <= 1'b0 ; wbs_rty_o <= 1'b0 ; end else begin if (wbs_ack_o) wbs_ack_o <= wbs_ack_i | ~wbs_stb_i ; else wbs_ack_o <= wbs_ack_i ; if (wbs_err_o) wbs_err_o <= ~wbs_stb_i ; else wbs_err_o <= wbs_err_i ; `ifdef PCI_WBS_B3_RTY_DISABLE wbs_rty_o <= 1'b0 ; `else if (wbs_rty_o) wbs_rty_o <= ~wbs_stb_i ; else wbs_rty_o <= wbs_rty_i ; `endif endendassign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) | (wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i != 3'b111) | (wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;endmodule</pre><hr /><address><span style="font-size: smaller">FreeBSD-CVSweb <<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>></span></address></body></html><!-- pf_body_end --></td><td><img width=15 src="/images/dotty.gif"></td></tr></table><xcenter><p><table width=100% cellpadding=0 cellspacing=0 border=0> <tr><td align=right valign=bottom><a title='Top' href='#top'><img border=0 alt='Top' src='/images/hr_up.gif'></a></td></tr> <tr><td background='/images/hpd.gif'><img height=1 border=0 src='/images/dotty.gif'></td></tr><tr><td height=4><img height=4 src='/images/dotty.gif'></td></tr></table> <br><!--<table border=0 cellpadding=0 cellspacing=1 bgcolor=#ffffff><tr><td><table cellpadding=0 cellspacing=0 border=0 bgcolor=#ffffff><tr><td>//--><script type="text/javascript"><!--google_ad_client = "pub-9285819221080148";google_alternate_color = "FFFFFF";google_ad_width = 728;google_ad_height = 90;google_ad_format = "728x90_as";google_ad_type = "text_image";google_ad_channel ="3034172958";google_color_border = "ffffff";google_color_bg = "ffffff";google_color_link = "444488";google_color_url = "b00000";google_color_text = "666666";//--></script><script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"></script><!--</td></tr></table></td></tr></table>//--></center><img border=0 src="/images/dotty.gif" height=1 width=400><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30></td></tr></table> </td></tr><tr bgcolor=#000000><td><img height=1 src="/images/dotty.gif"></td></tr></table><table background="/images/topbg.gif" width=100% cellpadding=0 cellspacing=0 border=0 bgcolor=#aaddff><tr><td align=right>Copyright (c) 1999-2007 OPENCORES.ORG. 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