📄 pci_wb_tpram.v
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Two-Port Sync RAM (*) //////// - Virage 2-port Sync RAM //////// //////// Supported FPGA RAMs are: //////// - Xilinx Virtex RAMB4_S16_S16 //////// //////// To Do: //////// - fix Avant! //////// - xilinx rams need external tri-state logic //////// - add additional RAMs (Altera, VS etc) //////// //////// Author(s): //////// - Damjan Lampret, lampret@opencores.org //////// - Miha Dolenc, mihad@opencores.org //////// ////////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2000 Authors and OPENCORES.ORG //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: pci_wb_tpram.v,v $// Revision 1.4 2004/08/19 15:27:34 mihad// Changed minimum pci image size to 256 bytes because// of some PC system problems with size of IO images.//// Revision 1.3 2003/10/17 09:11:52 markom// mbist signals updated according to newest convention//// Revision 1.2 2003/08/14 13:06:03 simons// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.//// Revision 1.1 2003/01/27 16:49:31 mihad// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.//// Revision 1.7 2002/10/18 03:36:37 tadejm// Changed wrong signal name mbist_sen into mbist_ctrl_i.//// Revision 1.6 2002/10/17 22:49:22 tadejm// Changed BIST signals for RAMs.//// Revision 1.5 2002/10/11 10:09:01 mihad// Added additional testcase and changed rst name in BIST to trst//// Revision 1.4 2002/10/08 17:17:06 mihad// Added BIST signals for RAMs.//// Revision 1.3 2002/09/30 17:22:27 mihad// Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!//// Revision 1.2 2002/08/19 16:51:36 mihad// Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives//// Revision 1.1 2002/02/01 14:43:31 mihad// *** empty log message ***////// synopsys translate_off`include "timescale.v"// synopsys translate_on`include "pci_constants.v"module pci_wb_tpram( // Generic synchronous two-port RAM interface clk_a, rst_a, ce_a, we_a, oe_a, addr_a, di_a, do_a, clk_b, rst_b, ce_b, we_b, oe_b, addr_b, di_b, do_b`ifdef PCI_BIST , // debug chain signals mbist_si_i, // bist scan serial in mbist_so_o, // bist scan serial out mbist_ctrl_i // bist chain shift control`endif);//// Default address and data buses width//parameter aw = 8;parameter dw = 40;//// Generic synchronous two-port RAM interface//input clk_a; // Clockinput rst_a; // Resetinput ce_a; // Chip enable inputinput we_a; // Write enable inputinput oe_a; // Output enable inputinput [aw-1:0] addr_a; // address bus inputsinput [dw-1:0] di_a; // input data busoutput [dw-1:0] do_a; // output data businput clk_b; // Clockinput rst_b; // Resetinput ce_b; // Chip enable inputinput we_b; // Write enable inputinput oe_b; // Output enable inputinput [aw-1:0] addr_b; // address bus inputsinput [dw-1:0] di_b; // input data busoutput [dw-1:0] do_b; // output data bus`ifdef PCI_BIST// debug chain signalsinput mbist_si_i; // bist scan serial inoutput mbist_so_o; // bist scan serial outinput [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i; // bist chain shift control`endif//// Internal wires and registers//`ifdef WB_VS_STP `define PCI_WB_RAM_SELECTED `ifdef PCI_BIST vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist `else vs_hdtp_64x40 i_vs_hdtp_64x40 `endif ( .RCK (clk_b), .WCK (clk_a), .RADR (addr_b), .WADR (addr_a), .DI (di_a), .DOUT (do_b), .REN (1'b0), .WEN (!we_a) `ifdef PCI_BIST , // debug chain signals .mbist_si_i (mbist_si_i), .mbist_so_o (mbist_so_o), .mbist_ctrl_i (mbist_ctrl_i) `endif ); assign do_a = 0 ;`endif`ifdef WB_ARTISAN_SDP `define PCI_WB_RAM_SELECTED // // Instantiation of ASIC memory: // // Artisan Synchronous Double-Port RAM (ra2sh) // `ifdef PCI_BIST art_hsdp_64x40_bist /*#(dw, 1<<aw, aw) */ artisan_sdp ( .QA(do_a), .CLKA(clk_a), .CENA(~ce_a), .WENA(~we_a), .AA(addr_a), .DA(di_a), .OENA(~oe_a),⌨️ 快捷键说明
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