📄 pci_delayed_sync(1).v
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<tr><td><font size=-2> </font></td></tr> <tr><td bgcolor="#347FB8"> <img src="/images/bullet.gif"> <font class=menu_section>Tools</font> </td></tr> <tr><td> <li class=small> <font class=menu_item><a href="/search.cgi">Search</a><br><table><tr><form action=/search.cgi/do_search><td><font class=small> </font></td><td><input class=searchfield type=text name=query></td></form></tr></table></font></li> </td></tr> <tr><td> <li class=small> <a class=menu_item href="/cvsget.shtml"><font class=menu_item>Download Cores (CVSGet)</font></a></li> </td></tr> <tr><td><font size=-2> </font></td></tr> <tr><td bgcolor="#347FB8"> <img src="/images/bullet.gif"> <font class=menu_section>More</font> </td></tr> <tr><td> <li class=small> <a class=menu_item href="/projects.cgi/web/wishbone/"><font class=menu_item>Wishbone</font></a></li> </td></tr> <tr><td> <li class=small> <a class=menu_item href="/projects.cgi/web/perlilog/"><font class=menu_item>Perlilog</font></a></li> </td></tr> <tr><td> <li class=small> <a class=menu_item href="/projects.cgi/web/edatools/"><font class=menu_item>EDA tools</font></a></li> </td></tr> <tr><td> <li class=small> <a class=menu_item href="/projects.cgi/web/opentech/"><font class=menu_item>OpenTech CD</font></a></li> </td></tr> <tr><td><font size=-2> </font></td></tr> </table></td><td width=10><img width=10 src="/images/dotty.gif"></td><td background="/images/vpd.gif"><img width=1 src="/images/dotty.gif"></td><td width=10><img width=10 src="/images/dotty.gif"></td><td valign=top> <table width=100% cellpadding=2 cellspacing=0 border=0> <tr><td><img height=2 src="/images/dotty.gif"></td></tr> </table> <table width=100% cellspacing=0 cellpadding=0 border=0><tr><td><!-- pf_body_start --> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html><head><title>pci/rtl/verilog/pci_delayed_sync.v - view - 1.3</title><meta name="robots" content="nofollow" /><meta name="generator" content="FreeBSD-CVSweb 3.0.5" /><meta http-equiv="Content-Script-Type" content="text/javascript" /><meta http-equiv="Content-Style-Type" content="text/css" /><link rel="stylesheet" type="text/css" href="/css/cvsweb.css" /></head><body class="src"><table class="navigate-header" width="100%" summary="Navigation"> <tr> <td><a href="./pci_delayed_sync.v#rev1.3"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_delayed_sync.v#rev1.3">pci_delayed_sync.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td> <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td> </tr></table><hr /><div class="log-markup">File: <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_delayed_sync.v">pci_delayed_sync.v</a><br /><a name="rev1.3"></a><a name="wb2hpi"></a><a name="rel_WB_B3"></a><a name="rel_9"></a><a name="rel_8"></a><a name="rel_7"></a><a name="rel_6"></a><a name="rel_13"></a><a name="rel_12"></a><a name="rel_11"></a><a name="rel_10"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a> Revision <b>1.3</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_delayed_sync.v?rev=1.3;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_delayed_sync.v?rev=1.3;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_delayed_sync.v?annotate=1.3">annotated</a> - <a href="pci_delayed_sync.v?r1=1.3#rev1.3">select for diffs</a><br /><i>Thu Aug 14 13:06:02 2003 UTC</i> (3 years, 9 months ago) by <i>simons</i><br />Branches: <a href="./pci_delayed_sync.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_delayed_sync.v?only_with_tag=wb2hpi">wb2hpi</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_9">rel_9</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_8">rel_8</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_7">rel_7</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_6">rel_6</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_13">rel_13</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_12">rel_12</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_11">rel_11</a>,<a href="./pci_delayed_sync.v?only_with_tag=rel_10">rel_10</a>,<a href="./pci_delayed_sync.v?only_with_tag=asyst_3">asyst_3</a>,<a href="./pci_delayed_sync.v?only_with_tag=asyst_2">asyst_2</a>,<a href="./pci_delayed_sync.v?only_with_tag=HEAD">HEAD</a><br /><pre class="log">synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.</pre></div><hr /><pre>////////////////////////////////////////////////////////////////////////// //////// File name "delayed_sync.v" //////// //////// This file is part of the "PCI bridge" project //////// http://www.opencores.org/cores/pci/ //////// //////// Author(s): //////// - Miha Dolenc (mihad@opencores.org) //////// //////// All additional information is avaliable in the README //////// file. //////// //////// ////////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: pci_delayed_sync.v,v $// Revision 1.3 2003/08/14 13:06:02 simons// synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.//// Revision 1.2 2003/03/26 13:16:18 mihad// Added the reset value parameter to the synchronizer flop module.// Added resets to all synchronizer flop instances.// Repaired initial sync value in fifos.//// Revision 1.1 2003/01/27 16:49:31 mihad// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.//// Revision 1.5 2002/09/25 09:54:50 mihad// Added completion expiration test for WB Slave unit. Changed expiration signalling//// Revision 1.4 2002/03/05 11:53:47 mihad// Added some testcases, removed un-needed fifo signals//// Revision 1.3 2002/02/01 15:25:12 mihad// Repaired a few bugs, updated specification, added test bench files and design document//// Revision 1.2 2001/10/05 08:14:28 mihad// Updated all files with inclusion of timescale file for simulation purposes.//// Revision 1.1.1.1 2001/10/02 15:33:46 mihad// New project directory structure////// module provides synchronization mechanism between requesting and completing side of the bridge`include "pci_constants.v"`include "bus_commands.v"// synopsys translate_off`include "timescale.v"// synopsys translate_onmodule pci_delayed_sync( reset_in, req_clk_in, comp_clk_in, req_in, comp_in, done_in, in_progress_in, comp_req_pending_out, req_req_pending_out, req_comp_pending_out, comp_comp_pending_out, addr_in, be_in, addr_out, be_out, we_in, we_out, bc_in, bc_out, status_in, status_out, comp_flush_out, burst_in, burst_out, retry_expired_in);// system inputsinput reset_in, // reset input req_clk_in, // requesting clock input comp_clk_in ; // completing clock input// request, completion, done and in progress indication inputsinput req_in, // request qualifier - when 1 it indicates that valid request data is provided on inputs comp_in, // completion qualifier - when 1, completing side indicates that request has completed done_in, // done input - when 1 indicates that requesting side of the bridge has completed a transaction on requesting bus in_progress_in ; // in progress indicator - indicates that current completion is in progress on requesting side of the bridge// pending indication outputsoutput comp_req_pending_out, // completion side request output - resynchronized from requesting clock to completing clock req_req_pending_out, // request pending output for requesting side req_comp_pending_out, // completion pending output for requesting side of the bridge - it indicates when completion is ready for completing on requesting bus comp_comp_pending_out ; // completion pending output for completing side of the bridge// additional signals and wires for clock domain passage of signalsreg comp_req_pending, req_req_pending, req_comp_pending, req_comp_pending_sample, comp_comp_pending, req_done_reg, comp_done_reg_main, comp_done_reg_clr, req_rty_exp_reg, req_rty_exp_clr, comp_rty_exp_reg, comp_rty_exp_clr ;wire sync_comp_req_pending, sync_req_comp_pending, sync_comp_done, sync_req_rty_exp, sync_comp_rty_exp_clr ;// inputs from requesting side - only this side can set address, bus command, byte enables, write enable and burst - outputs are common for both sides// all signals that identify requests are stored in this moduleinput [31:0] addr_in ; // address bus inputinput [3:0] be_in ; // byte enable inputinput we_in ; // write enable input - read/write request indication 1 = write request / 0 = read requestinput [3:0] bc_in ; // bus command inputinput burst_in ; // burst indicator - qualifies operation as burst/single transfer 1 = burst / 0 = single transfer// common request outputs used both by completing and requesting sides// this outputs are not resynchronized, since flags determine the request statusoutput [31:0] addr_out ;output [3:0] be_out ;output we_out ;output [3:0] bc_out ;output burst_out ;// completion side signals encoded termination status - 0 = normal completion / 1 = error terminated completioninput status_in ;output status_out ;// input signals that delayed transaction has been retried for max number of times// on this signal request is ditched, otherwise it would cause a deadlock// requestor can issue another request and procedure will be repeatedinput retry_expired_in ;// completion flush output - if in 2^^16 clock cycles transaction is not repeated by requesting agent - flush completion dataoutput comp_flush_out ;// output registers for common signalsreg [31:0] addr_out ;reg [3:0] be_out ;reg we_out ;reg [3:0] bc_out ;reg burst_out ;// delayed transaction information is stored only when request is issued and request nor completion are pendingwire new_request = req_in && ~req_comp_pending_out && ~req_req_pending_out ;always@(posedge req_clk_in or posedge reset_in)begin if (reset_in) begin addr_out <= #`FF_DELAY 32'h0000_0000 ; be_out <= #`FF_DELAY 4'h0 ; we_out <= #`FF_DELAY 1'b0 ; bc_out <= #`FF_DELAY `BC_RESERVED0 ; burst_out <= #`FF_DELAY 1'b0 ; end else if (new_request) begin addr_out <= #`FF_DELAY addr_in ; be_out <= #`FF_DELAY be_in ; we_out <= #`FF_DELAY we_in ; bc_out <= #`FF_DELAY bc_in ; burst_out <= #`FF_DELAY burst_in ; endend// completion pending cycle counterreg [16:0] comp_cycle_count ;/*=================================================================================================================================Passing of requests between clock domains:request originates on requesting side. It's then synchronized with two flip-flops to cross to completing clock domain=================================================================================================================================*/// main request flip-flop triggered on requesting side's clock// request is cleared whenever completion or retry expired is signalled from opposite side of the bridge⌨️ 快捷键说明
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