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view: <a href="pci_bridge32.v?rev=1.19;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.19;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.19">annotated</a> - <a href="pci_bridge32.v?r1=1.19#rev1.19">select for diffs</a><br /><i>Thu Sep 23 13:48:53 2004 UTC</i> (2 years, 7 months ago) by <i>mihad</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=HEAD">HEAD</a><br />Diff to previous 1.18: <a href="pci_bridge32.v.diff?r1=1.18;r2=1.19">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.18;r2=1.19;f=u">unified</a><br />Changes since revision 1.18: +31 -20 lines<br /><pre class="log">The control inputs from PCI are now muxed with control outputsusing output enable state for given signal.</pre><hr /><a name="rev1.18"></a> Revision <b>1.18</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.18;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.18;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.18;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.18">annotated</a> - <a href="pci_bridge32.v?r1=1.18#rev1.18">select for diffs</a><br /><i>Thu Aug 19 15:27:34 2004 UTC</i> (2 years, 8 months ago) by <i>mihad</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />Diff to previous 1.17: <a href="pci_bridge32.v.diff?r1=1.17;r2=1.18">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.17;r2=1.18;f=u">unified</a><br />Changes since revision 1.17: +53 -36 lines<br /><pre class="log">Changed minimum pci image size to 256 bytes becauseof some PC system problems with size of IO images.</pre><hr /><a name="rev1.17"></a><a name="wb2hpi"></a> Revision <b>1.17</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.17;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.17;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.17;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.17">annotated</a> - <a href="pci_bridge32.v?r1=1.17#rev1.17">select for diffs</a><br /><i>Sat Jan 24 11:54:18 2004 UTC</i> (3 years, 3 months ago) by <i>mihad</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=wb2hpi">wb2hpi</a><br />Diff to previous 1.16: <a href="pci_bridge32.v.diff?r1=1.16;r2=1.17">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.16;r2=1.17;f=u">unified</a><br />Changes since revision 1.16: +74 -33 lines<br /><pre class="log">Update! SPOCI Implemented!</pre><hr /><a name="rev1.16"></a><a name="rel_13"></a><a name="asyst_3"></a><a name="asyst_2"></a> Revision <b>1.16</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.16;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.16;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.16;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.16">annotated</a> - <a href="pci_bridge32.v?r1=1.16#rev1.16">select for diffs</a><br /><i>Fri Dec 19 11:11:30 2003 UTC</i> (3 years, 4 months ago) by <i>mihad</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=rel_13">rel_13</a>,<a href="./pci_bridge32.v?only_with_tag=asyst_3">asyst_3</a>,<a href="./pci_bridge32.v?only_with_tag=asyst_2">asyst_2</a><br />Diff to previous 1.15: <a href="pci_bridge32.v.diff?r1=1.15;r2=1.16">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.15;r2=1.16;f=u">unified</a><br />Changes since revision 1.15: +18 -11 lines<br /><pre class="log">Compact PCI Hot Swap support added.New testcases added.Specification updated.Test application changed to support WB B3 cycles.</pre><hr /><a name="rev1.15"></a> Revision <b>1.15</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.15;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.15;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.15;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.15">annotated</a> - <a href="pci_bridge32.v?r1=1.15#rev1.15">select for diffs</a><br /><i>Wed Dec 10 12:02:54 2003 UTC</i> (3 years, 5 months ago) by <i>mihad</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />Diff to previous 1.14: <a href="pci_bridge32.v.diff?r1=1.14;r2=1.15">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.14;r2=1.15;f=u">unified</a><br />Changes since revision 1.14: +33 -1 lines<br /><pre class="log">The wbs B3 to B2 translation logic had wrong reset wire connected!</pre><hr /><a name="rev1.14"></a><a name="rel_12"></a> Revision <b>1.14</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.14;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.14;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.14;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.14">annotated</a> - <a href="pci_bridge32.v?r1=1.14#rev1.14">select for diffs</a><br /><i>Tue Dec 9 09:33:57 2003 UTC</i> (3 years, 5 months ago) by <i>simons</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=rel_12">rel_12</a><br />Diff to previous 1.13: <a href="pci_bridge32.v.diff?r1=1.13;r2=1.14">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.13;r2=1.14;f=u">unified</a><br />Changes since revision 1.13: +3 -4 lines<br /><pre class="log">Some warning cleanup.</pre><hr /><a name="rev1.13"></a><a name="rel_9"></a><a name="rel_11"></a><a name="rel_10"></a> Revision <b>1.13</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.13;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.13;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.13;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.13">annotated</a> - <a href="pci_bridge32.v?r1=1.13#rev1.13">select for diffs</a><br /><i>Fri Oct 17 09:11:52 2003 UTC</i> (3 years, 7 months ago) by <i>markom</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=rel_9">rel_9</a>,<a href="./pci_bridge32.v?only_with_tag=rel_11">rel_11</a>,<a href="./pci_bridge32.v?only_with_tag=rel_10">rel_10</a><br />Diff to previous 1.12: <a href="pci_bridge32.v.diff?r1=1.12;r2=1.13">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.12;r2=1.13;f=u">unified</a><br />Changes since revision 1.12: +16 -21 lines<br /><pre class="log">mbist signals updated according to newest convention</pre><hr /><a name="rev1.12"></a><a name="rel_WB_B3"></a><a name="rel_8"></a> Revision <b>1.12</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.12;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.12;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.12;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.12">annotated</a> - <a href="pci_bridge32.v?r1=1.12#rev1.12">select for diffs</a><br /><i>Thu Aug 21 20:49:03 2003 UTC</i> (3 years, 8 months ago) by <i>tadejm</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,<a href="./pci_bridge32.v?only_with_tag=rel_8">rel_8</a><br />Diff to previous 1.11: <a href="pci_bridge32.v.diff?r1=1.11;r2=1.12">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.11;r2=1.12;f=u">unified</a><br />Changes since revision 1.11: +24 -16 lines<br /><pre class="log">Added signals for WB Master B3.</pre><hr /><a name="rev1.11"></a><a name="rel_7"></a><a name="rel_6"></a> Revision <b>1.11</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.11;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.11;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.11;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.11">annotated</a> - <a href="pci_bridge32.v?r1=1.11#rev1.11">select for diffs</a><br /><i>Fri Aug 8 16:36:33 2003 UTC</i> (3 years, 9 months ago) by <i>tadejm</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=rel_7">rel_7</a>,<a href="./pci_bridge32.v?only_with_tag=rel_6">rel_6</a><br />Diff to previous 1.10: <a href="pci_bridge32.v.diff?r1=1.10;r2=1.11">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.10;r2=1.11;f=u">unified</a><br />Changes since revision 1.10: +6 -0 lines<br /><pre class="log">Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure.</pre><hr /><a name="rev1.10"></a> Revision <b>1.10</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.10;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.10;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.10;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.10">annotated</a> - <a href="pci_bridge32.v?r1=1.10#rev1.10">select for diffs</a><br /><i>Sun Aug 3 18:05:06 2003 UTC</i> (3 years, 9 months ago) by <i>mihad</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />Diff to previous 1.9: <a href="pci_bridge32.v.diff?r1=1.9;r2=1.10">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.9;r2=1.10;f=u">unified</a><br />Changes since revision 1.9: +109 -7 lines<br /><pre class="log">Added limited WISHBONE B3 support for WISHBONE Slave Unit.Doesn't support full speed bursts yet.</pre><hr /><a name="rev1.9"></a><a name="rel_5"></a><a name="rel_4"></a> Revision <b>1.9</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.9;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.9;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.9;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.9">annotated</a> - <a href="pci_bridge32.v?r1=1.9#rev1.9">select for diffs</a><br /><i>Mon Jan 27 16:49:31 2003 UTC</i> (4 years, 3 months ago) by <i>mihad</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=rel_5">rel_5</a>,<a href="./pci_bridge32.v?only_with_tag=rel_4">rel_4</a><br />Diff to previous 1.8: <a href="pci_bridge32.v.diff?r1=1.8;r2=1.9">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.8;r2=1.9;f=u">unified</a><br />Changes since revision 1.8: +237 -234 lines<br /><pre class="log">Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.</pre><hr /><a name="rev1.8"></a><a name="rel_3"></a><a name="rel_2"></a> Revision <b>1.8</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_bridge32.v?rev=1.8;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_bridge32.v?rev=1.8;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_bridge32.v?rev=1.8;content-type=text%2Fx-cvsweb-markup" class="display-link">markup</a>, <a href="pci_bridge32.v?annotate=1.8">annotated</a> - <a href="pci_bridge32.v?r1=1.8#rev1.8">select for diffs</a><br /><i>Mon Oct 21 13:04:33 2002 UTC</i> (4 years, 6 months ago) by <i>mihad</i><br />Branches: <a href="./pci_bridge32.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_bridge32.v?only_with_tag=rel_3">rel_3</a>,<a href="./pci_bridge32.v?only_with_tag=rel_2">rel_2</a><br />Diff to previous 1.7: <a href="pci_bridge32.v.diff?r1=1.7;r2=1.8">preferred</a>, <a href="pci_bridge32.v.diff?r1=1.7;r2=1.8;f=u">unified</a><br />Changes since revision 1.7: +5 -2 lines<br /><pre class="log">Changed BIST signal names etc..</pre><hr />⌨️ 快捷键说明
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