pci_bridge32(1).v

PCI-master的核

wire    [3:0]   pciu_err_be_out ;
wire            pciu_err_signal_out ;
wire            pciu_err_source_out ;
wire            pciu_err_rty_exp_out ;
wire    [11:0]  pciu_conf_offset_out ;
wire            pciu_conf_renable_out ;
wire            pciu_conf_wenable_out ;
wire    [3:0]   pciu_conf_be_out ;
wire    [31:0]  pciu_conf_data_out ;
wire            pciu_pci_drcomp_pending_out ;
wire            pciu_pciw_fifo_empty_out ;

// assign pci target unit's outputs to top outputs where possible
assign wbm_adr_o    =   pciu_adr_out ;
assign wbm_dat_o    =   pciu_mdata_out ;
assign wbm_cyc_o    =   pciu_cyc_out ;
assign wbm_stb_o    =   pciu_stb_out ;
assign wbm_we_o     =   pciu_we_out ;
assign wbm_cti_o    =   pciu_cti_out ;
assign wbm_bte_o    =   pciu_bte_out ;
assign wbm_sel_o    =   pciu_sel_out ;

// CONFIGURATION SPACE OUTPUTS
wire    [31:0]  conf_w_data_out ;
wire    [31:0]  conf_r_data_out ;
wire            conf_serr_enable_out ;
wire            conf_perr_response_out ;
wire            conf_pci_master_enable_out ;
wire            conf_mem_space_enable_out ;
wire            conf_io_space_enable_out ;
wire    [7:0]   conf_cache_line_size_to_pci_out ;
wire    [7:0]   conf_cache_line_size_to_wb_out ;
wire            conf_cache_lsize_not_zero_to_wb_out ;
wire    [7:0]   conf_latency_tim_out ;

wire    [pci_ba0_width   - 1:0]   conf_pci_ba0_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ba1_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ba2_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ba3_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ba4_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ba5_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ta0_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ta1_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ta2_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ta3_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ta4_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_ta5_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_am0_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_am1_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_am2_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_am3_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_am4_out ;
wire    [pci_ba1_5_width - 1:0]   conf_pci_am5_out ;

wire            conf_pci_mem_io0_out ;
wire            conf_pci_mem_io1_out ;
wire            conf_pci_mem_io2_out ;
wire            conf_pci_mem_io3_out ;
wire            conf_pci_mem_io4_out ;
wire            conf_pci_mem_io5_out ;

wire    [1:0]   conf_pci_img_ctrl0_out ;
wire    [1:0]   conf_pci_img_ctrl1_out ;
wire    [1:0]   conf_pci_img_ctrl2_out ;
wire    [1:0]   conf_pci_img_ctrl3_out ;
wire    [1:0]   conf_pci_img_ctrl4_out ;
wire    [1:0]   conf_pci_img_ctrl5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba0_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba1_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba2_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba3_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba4_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ba5_out ;

wire            conf_wb_mem_io0_out ;
wire            conf_wb_mem_io1_out ;
wire            conf_wb_mem_io2_out ;
wire            conf_wb_mem_io3_out ;
wire            conf_wb_mem_io4_out ;
wire            conf_wb_mem_io5_out ;

wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am0_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am1_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am2_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am3_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am4_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_am5_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta0_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta1_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta2_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta3_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta4_out ;
wire    [19:(20 - `WB_NUM_OF_DEC_ADDR_LINES)]  conf_wb_ta5_out ;
wire    [2:0]   conf_wb_img_ctrl0_out ;
wire    [2:0]   conf_wb_img_ctrl1_out ;
wire    [2:0]   conf_wb_img_ctrl2_out ;
wire    [2:0]   conf_wb_img_ctrl3_out ;
wire    [2:0]   conf_wb_img_ctrl4_out ;
wire    [2:0]   conf_wb_img_ctrl5_out ;
wire    [23:0]  conf_ccyc_addr_out ;
wire            conf_soft_res_out ;
wire            conf_int_out ;
wire            conf_wb_init_complete_out  ;
wire            conf_pci_init_complete_out ;

// PCI IO MUX OUTPUTS
wire        pci_mux_frame_out ;
wire        pci_mux_irdy_out ;
wire        pci_mux_devsel_out ;
wire        pci_mux_trdy_out ;
wire        pci_mux_stop_out ;
wire [3:0]  pci_mux_cbe_out ;
wire [31:0] pci_mux_ad_out ;
wire        pci_mux_ad_load_out ;

wire [31:0] pci_mux_ad_en_out ;
wire        pci_mux_ad_en_unregistered_out ;
wire        pci_mux_frame_en_out ;
wire        pci_mux_irdy_en_out ;
wire        pci_mux_devsel_en_out ;
wire        pci_mux_trdy_en_out ;
wire        pci_mux_stop_en_out ;
wire [3:0]  pci_mux_cbe_en_out ;

wire        pci_mux_par_out ;
wire        pci_mux_par_en_out ;
wire        pci_mux_perr_out ;
wire        pci_mux_perr_en_out ;
wire        pci_mux_serr_out ;
wire        pci_mux_serr_en_out ;

wire        pci_mux_req_out ;
wire        pci_mux_req_en_out ;

// assign outputs to top level outputs

assign pci_ad_oe_o       = pci_mux_ad_en_out ;
assign pci_frame_oe_o   = pci_mux_frame_en_out ;
assign pci_irdy_oe_o    = pci_mux_irdy_en_out ;
assign pci_cbe_oe_o     = pci_mux_cbe_en_out ;

assign pci_par_o         =   pci_mux_par_out ;
assign pci_par_oe_o      =   pci_mux_par_en_out ;
assign pci_perr_o       =   pci_mux_perr_out ;
assign pci_perr_oe_o    =   pci_mux_perr_en_out ;
assign pci_serr_o       =   pci_mux_serr_out ;
assign pci_serr_oe_o    =   pci_mux_serr_en_out ;

assign pci_req_o        =   pci_mux_req_out ;
assign pci_req_oe_o     =   pci_mux_req_en_out ;

assign pci_trdy_oe_o    = pci_mux_trdy_en_out ;
assign pci_devsel_oe_o  = pci_mux_devsel_en_out ;
assign pci_stop_oe_o    = pci_mux_stop_en_out ;
assign pci_trdy_o       =  pci_mux_trdy_out ;
assign pci_devsel_o     = pci_mux_devsel_out ;
assign pci_stop_o       = pci_mux_stop_out ;

assign pci_ad_o          = pci_mux_ad_out ;
assign pci_frame_o      = pci_mux_frame_out ;
assign pci_irdy_o       = pci_mux_irdy_out ;
assign pci_cbe_o        = pci_mux_cbe_out ;

// duplicate output register's outputs
wire            out_bckp_frame_out ;
wire            out_bckp_irdy_out ;
wire            out_bckp_devsel_out ;
wire            out_bckp_trdy_out ;
wire            out_bckp_stop_out ;
wire    [3:0]   out_bckp_cbe_out ;
wire            out_bckp_cbe_en_out ;
wire    [31:0]  out_bckp_ad_out ;
wire            out_bckp_ad_en_out ;
wire            out_bckp_irdy_en_out ;
wire            out_bckp_frame_en_out ;
wire            out_bckp_tar_ad_en_out ;
wire            out_bckp_mas_ad_en_out ;
wire            out_bckp_trdy_en_out ;

wire            out_bckp_par_out ;
wire            out_bckp_par_en_out ;
wire            out_bckp_perr_out ;
wire            out_bckp_perr_en_out ;
wire            out_bckp_serr_out ;
wire            out_bckp_serr_en_out ;

wire            int_pci_frame   = out_bckp_frame_en_out ? out_bckp_frame_out  : pci_frame_i     ;
wire            int_pci_irdy    = out_bckp_irdy_en_out  ? out_bckp_irdy_out   : pci_irdy_i      ;
wire            int_pci_devsel  = out_bckp_trdy_en_out  ? out_bckp_devsel_out : pci_devsel_i    ;
wire            int_pci_trdy    = out_bckp_trdy_en_out  ? out_bckp_trdy_out   : pci_trdy_i      ;
wire            int_pci_stop    = out_bckp_trdy_en_out  ? out_bckp_stop_out   : pci_stop_i      ;
wire    [ 3: 0] int_pci_cbe     = out_bckp_cbe_en_out   ? out_bckp_cbe_out    : pci_cbe_i       ;
wire            int_pci_par     = out_bckp_par_en_out   ? out_bckp_par_out    : pci_par_i       ;
wire            int_pci_perr    = out_bckp_perr_en_out  ? out_bckp_perr_out   : pci_perr_i      ;
// PARITY CHECKER OUTPUTS
wire    parchk_pci_par_out ;
wire    parchk_pci_par_en_out ;
wire    parchk_pci_perr_out ;
wire    parchk_pci_perr_en_out ;
wire    parchk_pci_serr_out ;
wire    parchk_pci_serr_en_out ;
wire    parchk_par_err_detect_out ;
wire    parchk_perr_mas_detect_out ;
wire    parchk_sig_serr_out ;

// input register outputs
wire            in_reg_gnt_out ;
wire            in_reg_frame_out ;
wire            in_reg_irdy_out ;
wire            in_reg_trdy_out ;
wire            in_reg_stop_out ;
wire            in_reg_devsel_out ;
wire            in_reg_idsel_out ;
wire    [31:0]  in_reg_ad_out ;
wire    [3:0]   in_reg_cbe_out ;

/*=========================================================================================================
Now comes definition of all modules' and their appropriate inputs
=========================================================================================================*/
// PCI BRIDGE RESET AND INTERRUPT LOGIC INPUTS
wire    pci_resi_rst_i                  = wb_rst_i ;
wire    pci_resi_pci_rstn_in            = pci_rst_i ;
wire    pci_resi_conf_soft_res_in       = conf_soft_res_out ;
wire    pci_inti_pci_intan_in           = pci_inta_i ;
wire    pci_inti_conf_int_in            = conf_int_out ;
wire    pci_inti_int_i                  = wb_int_i ;
wire    pci_into_init_complete_in       = conf_pci_init_complete_out ;

pci_rst_int pci_resets_and_interrupts
(
    .clk_in                 (pci_clk),
    .rst_i                  (pci_resi_rst_i),
    .pci_rstn_in            (pci_resi_pci_rstn_in),
    .conf_soft_res_in       (pci_resi_conf_soft_res_in),
    .reset                  (pci_reso_reset),
    .pci_rstn_out           (pci_reso_pci_rstn_out),
    .pci_rstn_en_out        (pci_reso_pci_rstn_en_out),
    .rst_o                  (pci_reso_rst_o),
    .pci_intan_in           (pci_inti_pci_intan_in),
    .conf_int_in            (pci_inti_conf_int_in),
    .int_i                  (pci_inti_int_i),
    .pci_intan_out          (pci_into_pci_intan_out),
    .pci_intan_en_out       (pci_into_pci_intan_en_out),
    .int_o                  (pci_into_int_o),
    .conf_isr_int_prop_out  (pci_into_conf_isr_int_prop_out),
    .init_complete_in       (pci_into_init_complete_in)
);


`ifdef PCI_WB_REV_B3

wire            wbs_wbb3_2_wbb2_cyc_o   ;
wire            wbs_wbb3_2_wbb2_stb_o   ;
wire    [31:0]  wbs_wbb3_2_wbb2_adr_o   ;
wire    [31:0]  wbs_wbb3_2_wbb2_dat_i_o ;
wire    [31:0]  wbs_wbb3_2_wbb2_dat_o_o ;
wire            wbs_wbb3_2_wbb2_we_o    ;
wire    [ 3:0]  wbs_wbb3_2_wbb2_sel_o   ;
wire            wbs_wbb3_2_wbb2_ack_o   ;
wire            wbs_wbb3_2_wbb2_err_o   ;
wire            wbs_wbb3_2_wbb2_rty_o   ;
wire            wbs_wbb3_2_wbb2_cab_o   ;

// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o    =   wbs_wbb3_2_wbb2_dat_o_o ;
assign wbs_ack_o    =   wbs_wbb3_2_wbb2_ack_o   ;
assign wbs_rty_o    =   wbs_wbb3_2_wbb2_rty_o   ;
assign wbs_err_o    =   wbs_wbb3_2_wbb2_err_o       ;

wire            wbs_wbb3_2_wbb2_cyc_i   =   wbs_cyc_i       ;
wire            wbs_wbb3_2_wbb2_stb_i   =   wbs_stb_i       ;
wire            wbs_wbb3_2_wbb2_we_i    =   wbs_we_i        ;
wire            wbs_wbb3_2_wbb2_ack_i   =   wbu_ack_out     ;
wire            wbs_wbb3_2_wbb2_err_i   =   wbu_err_out     ;
wire            wbs_wbb3_2_wbb2_rty_i   =   wbu_rty_out     ;
wire    [31:0]  wbs_wbb3_2_wbb2_adr_i   =   wbs_adr_i       ;
wire    [ 3:0]  wbs_wbb3_2_wbb2_sel_i   =   wbs_sel_i       ;
wire    [31:0]  wbs_wbb3_2_wbb2_dat_i_i =   wbs_dat_i       ;
wire    [31:0]  wbs_wbb3_2_wbb2_dat_o_i =   wbu_sdata_out   ;
wire    [ 2:0]  wbs_wbb3_2_wbb2_cti_i   =   wbs_cti_i       ;
wire    [ 1:0]  wbs_wbb3_2_wbb2_bte_i   =   wbs_bte_i       ;

pci_wbs_wbb3_2_wbb2 i_pci_wbs_wbb3_2_wbb2
(
    .wb_clk_i           (   wb_clk_i    )   ,
    .wb_rst_i           (   reset       )   ,
                        
    .wbs_cyc_i          (   wbs_wbb3_2_wbb2_cyc_i       )   ,
    .wbs_cyc_o          (   wbs_wbb3_2_wbb2_cyc_o       )   ,
    .wbs_stb_i          (   wbs_wbb3_2_wbb2_stb_i       )   ,
    .wbs_stb_o          (   wbs_wbb3_2_wbb2_stb_o       )   ,
    .wbs_adr_i          (   wbs_wbb3_2_wbb2_adr_i       )   ,
    .wbs_adr_o          (   wbs_wbb3_2_wbb2_adr_o       )   ,
    .wbs_dat_i_i        (   wbs_wbb3_2_wbb2_dat_i_i     )   ,
    .wbs_dat_i_o        (   wbs_wbb3_2_wbb2_dat_i_o     )   ,
    .wbs_dat_o_i        (   wbs_wbb3_2_wbb2_dat_o_i     )   ,
    .wbs_dat_o_o        (   wbs_wbb3_2_wbb2_dat_o_o     )   ,
    .wbs_we_i           (   wbs_wbb3_2_wbb2_we_i        )   ,
    .wbs_we_o           (   wbs_wbb3_2_wbb2_we_o        )   ,
    .wbs_sel_i          (   wbs_wbb3_2_wbb2_sel_i       )   ,
    .wbs_sel_o          (   wbs_wbb3_2_wbb2_sel_o       )   ,
    .wbs_ack_i          (   wbs_wbb3_2_wbb2_ack_i       )   ,
    .wbs_ack_o          (   wbs_wbb3_2_wbb2_ack_o       )   ,
    .wbs_err_i          (   wbs_wbb3_2_wbb2_err_i       )   ,
    .wbs_err_o          (   wbs_wbb3_2_wbb2_err_o       )   ,
    .wbs_rty_i          (   wbs_wbb3_2_wbb2_rty_i       )   ,
    .wbs_rty_o          (   wbs_wbb3_2_wbb2_rty_o       )   ,
    .wbs_cti_i          (   wbs_wbb3_2_wbb2_cti_i       )   ,
    .wbs_bte_i          (   wbs_wbb3_2_wbb2_bte_i       )   ,
    .wbs_cab_o          (   wbs_wbb3_2_wbb2_cab_o       )   ,
    .wb_init_complete_i (   conf_wb_init_complete_out   )
) ;

// WISHBONE SLAVE UNIT INPUTS
wire    [31:0]  wbu_addr_in     =   wbs_wbb3_2_wbb2_adr_o   ;
wire    [31:0]  wbu_sdata_in    =   wbs_wbb3_2_wbb2_dat_i_o ;
wire            wbu_cyc_in      =   wbs_wbb3_2_wbb2_cyc_o   ;
wire            wbu_stb_in      =   wbs_wbb3_2_wbb2_stb_o   ;
wire            wbu_we_in       =   wbs_wbb3_2_wbb2_we_o    ;
wire    [3:0]   wbu_sel_in      =   wbs_wbb3_2_wbb2_sel_o   ;
wire            wbu_cab_in      =   wbs_wbb3_2_wbb2_cab_o   ;

`else

// WISHBONE SLAVE UNIT INPUTS
wire    [31:0]  wbu_addr_in                     =   wbs_adr_i ;
wire    [31:0]  wbu_sdata_in                    =   wbs_dat_i ;
wire            wbu_cyc_in                      =   wbs_cyc_i ;
wire            wbu_stb_in                      =   wbs_stb_i ;
wire            wbu_we_in                       =   wbs_we_i ;
wire    [3:0]   wbu_sel_in                      =   wbs_sel_i ;
wire            wbu_cab_in                      =   wbs_cab_i ;

// assign wishbone slave unit's outputs to top outputs where possible
assign wbs_dat_o    =   wbu_sdata_out   ;
assign wbs_ack_o    =   wbu_ack_out     ;
assign wbs_rty_o    =   wbu_rty_out     ;
assign wbs_err_o    =   wbu_err_out     ;

`endif