pci_bridge32(1).v

PCI-master的核

    wbs_err_o,

    // WISHBONE master interface
    wbm_adr_o,
    wbm_dat_i,
    wbm_dat_o,
    wbm_sel_o,
    wbm_cyc_o,
    wbm_stb_o,
    wbm_we_o,
    wbm_cti_o,
    wbm_bte_o,
    wbm_ack_i,
    wbm_rty_i,
    wbm_err_i,

    // pci interface - system pins
    pci_clk_i,
    pci_rst_i,
    pci_rst_o,
    pci_inta_i,
    pci_inta_o,
    pci_rst_oe_o,
    pci_inta_oe_o,

    // arbitration pins
    pci_req_o,
    pci_req_oe_o,

    pci_gnt_i,

    // protocol pins
    pci_frame_i,
    pci_frame_o,

    pci_frame_oe_o,
    pci_irdy_oe_o,
    pci_devsel_oe_o,
    pci_trdy_oe_o,
    pci_stop_oe_o,
    pci_ad_oe_o,
    pci_cbe_oe_o,

    pci_irdy_i,
    pci_irdy_o,

    pci_idsel_i,

    pci_devsel_i,
    pci_devsel_o,

    pci_trdy_i,
    pci_trdy_o,

    pci_stop_i,
    pci_stop_o          ,

    // data transfer pins
    pci_ad_i,
    pci_ad_o,

    pci_cbe_i,
    pci_cbe_o,

    // parity generation and checking pins
    pci_par_i,
    pci_par_o,
    pci_par_oe_o,

    pci_perr_i,
    pci_perr_o,
    pci_perr_oe_o,

    // system error pin
    pci_serr_o,
    pci_serr_oe_o

`ifdef PCI_BIST
    ,
    // debug chain signals
    mbist_si_i,       // bist scan serial in
    mbist_so_o,       // bist scan serial out
    mbist_ctrl_i        // bist chain shift control
`endif

`ifdef PCI_CPCI_HS_IMPLEMENT
    ,
    // Compact PCI Hot Swap signals
    pci_cpci_hs_enum_o      ,   //  ENUM# output with output enable (open drain)
    pci_cpci_hs_enum_oe_o   ,   //  ENUM# enum output enable
    pci_cpci_hs_led_o       ,   //  LED output with output enable (open drain)
    pci_cpci_hs_led_oe_o    ,   //  LED output enable
    pci_cpci_hs_es_i            //  ejector switch state indicator input
`endif

`ifdef PCI_SPOCI
    ,
    // Serial power on configuration interface
    spoci_scl_o     ,
    spoci_scl_oe_o  ,
    spoci_sda_i     ,
    spoci_sda_o     ,
    spoci_sda_oe_o
`endif

);

`ifdef HOST
    `ifdef NO_CNF_IMAGE
        parameter pci_ba0_width = `PCI_NUM_OF_DEC_ADDR_LINES ;
    `else
        parameter pci_ba0_width = 20    ;
    `endif
`endif

`ifdef GUEST
    parameter pci_ba0_width = 20 ;
`endif

parameter pci_ba1_5_width = `PCI_NUM_OF_DEC_ADDR_LINES ;

// WISHBONE system signals
input   wb_clk_i ;
input   wb_rst_i ;
output  wb_rst_o ;
input   wb_int_i ;
output  wb_int_o ;

// WISHBONE slave interface
input   [31:0]  wbs_adr_i ;
input   [31:0]  wbs_dat_i ;
output  [31:0]  wbs_dat_o ;
input   [3:0]   wbs_sel_i ;
input           wbs_cyc_i ;
input           wbs_stb_i ;
input           wbs_we_i ;

`ifdef PCI_WB_REV_B3

input [2:0] wbs_cti_i ;
input [1:0] wbs_bte_i ;

`else

input wbs_cab_i ;

`endif

output          wbs_ack_o ;
output          wbs_rty_o ;
output          wbs_err_o ;

// WISHBONE master interface
output  [31:0]  wbm_adr_o ;
input   [31:0]  wbm_dat_i ;
output  [31:0]  wbm_dat_o ;
output  [3:0]   wbm_sel_o ;
output          wbm_cyc_o ;
output          wbm_stb_o ;
output          wbm_we_o ;
output  [2:0]   wbm_cti_o ;
output  [1:0]   wbm_bte_o ;
input           wbm_ack_i ;
input           wbm_rty_i ;
input           wbm_err_i ;

// pci interface - system pins
input   pci_clk_i ;
input   pci_rst_i ;
output  pci_rst_o ;
output  pci_rst_oe_o ;

input   pci_inta_i ;
output  pci_inta_o ;
output  pci_inta_oe_o ;

// arbitration pins
output  pci_req_o ;
output  pci_req_oe_o ;

input   pci_gnt_i ;

// protocol pins
input   pci_frame_i ;
output  pci_frame_o ;
output  pci_frame_oe_o ;
output  pci_irdy_oe_o ;
output  pci_devsel_oe_o ;
output  pci_trdy_oe_o ;
output  pci_stop_oe_o ;
output  [31:0] pci_ad_oe_o ;
output  [3:0]  pci_cbe_oe_o ;

input   pci_irdy_i ;
output  pci_irdy_o ;

input   pci_idsel_i ;

input   pci_devsel_i ;
output  pci_devsel_o ;

input   pci_trdy_i ;
output  pci_trdy_o ;

input   pci_stop_i ;
output  pci_stop_o ;

// data transfer pins
input   [31:0]  pci_ad_i ;
output  [31:0]  pci_ad_o ;

input   [3:0]   pci_cbe_i ;
output  [3:0]   pci_cbe_o ;

// parity generation and checking pins
input   pci_par_i ;
output  pci_par_o ;
output  pci_par_oe_o ;

input   pci_perr_i ;
output  pci_perr_o ;
output  pci_perr_oe_o ;

// system error pin
output  pci_serr_o ;
output  pci_serr_oe_o ;

`ifdef PCI_BIST
/*-----------------------------------------------------
BIST debug chain port signals
-----------------------------------------------------*/
input   mbist_si_i;       // bist scan serial in
output  mbist_so_o;       // bist scan serial out
input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
`endif

`ifdef PCI_CPCI_HS_IMPLEMENT
    // Compact PCI Hot Swap signals
output  pci_cpci_hs_enum_o      ;   //  ENUM# output with output enable (open drain)
output  pci_cpci_hs_enum_oe_o   ;   //  ENUM# enum output enable
output  pci_cpci_hs_led_o       ;   //  LED output with output enable (open drain)
output  pci_cpci_hs_led_oe_o    ;   //  LED output enable
input   pci_cpci_hs_es_i        ;   //  ejector switch state indicator input

assign  pci_cpci_hs_enum_o = 1'b0   ;
assign  pci_cpci_hs_led_o  = 1'b0   ;
`endif

`ifdef PCI_SPOCI
output  spoci_scl_o     ;
output  spoci_scl_oe_o  ;
input   spoci_sda_i     ;
output  spoci_sda_o     ;
output  spoci_sda_oe_o  ;

assign  spoci_scl_o = 1'b0  ;
assign  spoci_sda_o = 1'b0  ;
`endif

// declare clock and reset wires
wire pci_clk = pci_clk_i ;
wire wb_clk  = wb_clk_i ;
wire reset ; // assigned at pci bridge reset and interrupt logic

/*=========================================================================================================
First comes definition of all modules' outputs, so they can be assigned to any other module's input later
  in the file, when module is instantiated
=========================================================================================================*/
// PCI BRIDGE RESET AND INTERRUPT LOGIC OUTPUTS
wire    pci_reso_reset ;
wire    pci_reso_pci_rstn_out ;
wire    pci_reso_pci_rstn_en_out ;
wire    pci_reso_rst_o ;
wire    pci_into_pci_intan_out ;
wire    pci_into_pci_intan_en_out ;
wire    pci_into_int_o ;
wire    pci_into_conf_isr_int_prop_out ;

// assign pci bridge reset interrupt logic outputs to top outputs where possible
assign reset            = pci_reso_reset ;
assign pci_rst_o     = pci_reso_pci_rstn_out ;
assign pci_rst_oe_o  = pci_reso_pci_rstn_en_out ;
assign wb_rst_o         = pci_reso_rst_o ;
assign pci_inta_o    = pci_into_pci_intan_out ;
assign pci_inta_oe_o = pci_into_pci_intan_en_out ;
assign wb_int_o         = pci_into_int_o ;

// WISHBONE SLAVE UNIT OUTPUTS
wire    [31:0]  wbu_sdata_out ;
wire            wbu_ack_out ;
wire            wbu_rty_out ;
wire            wbu_err_out ;
wire            wbu_pciif_req_out ;
wire            wbu_pciif_frame_out ;
wire            wbu_pciif_frame_en_out ;
wire            wbu_pciif_irdy_out ;
wire            wbu_pciif_irdy_en_out ;
wire    [31:0]  wbu_pciif_ad_out ;
wire            wbu_pciif_ad_en_out ;
wire    [3:0]   wbu_pciif_cbe_out ;
wire            wbu_pciif_cbe_en_out ;
wire    [31:0]  wbu_err_addr_out ;
wire    [3:0]   wbu_err_bc_out ;
wire            wbu_err_signal_out ;
wire            wbu_err_source_out ;
wire            wbu_err_rty_exp_out ;
wire            wbu_tabort_rec_out ;
wire            wbu_mabort_rec_out ;
wire    [11:0]  wbu_conf_offset_out ;
wire            wbu_conf_renable_out ;
wire            wbu_conf_wenable_out ;
wire    [3:0]   wbu_conf_be_out ;
wire    [31:0]  wbu_conf_data_out ;
wire            wbu_del_read_comp_pending_out ;
wire            wbu_wbw_fifo_empty_out ;
wire            wbu_ad_load_out ;
wire            wbu_ad_load_on_transfer_out ;
wire            wbu_pciif_frame_load_out ;

// PCI TARGET UNIT OUTPUTS
wire    [31:0]  pciu_adr_out ;
wire    [31:0]  pciu_mdata_out ;
wire            pciu_cyc_out ;
wire            pciu_stb_out ;
wire            pciu_we_out ;
wire    [2:0]   pciu_cti_out ;
wire    [1:0]   pciu_bte_out ;
wire    [3:0]   pciu_sel_out ;
wire            pciu_pciif_trdy_out ;
wire            pciu_pciif_stop_out ;
wire            pciu_pciif_devsel_out ;
wire            pciu_pciif_trdy_en_out ;
wire            pciu_pciif_stop_en_out ;
wire            pciu_pciif_devsel_en_out ;
wire            pciu_ad_load_out ;
wire            pciu_ad_load_on_transfer_out ;
wire   [31:0]   pciu_pciif_ad_out ;
wire            pciu_pciif_ad_en_out ;
wire            pciu_pciif_tabort_set_out ;
wire    [31:0]  pciu_err_addr_out ;
wire    [3:0]   pciu_err_bc_out ;
wire    [31:0]  pciu_err_data_out ;