📄 pci_conf_cyc_addr_dec(1).v
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view - 1.1</title><meta name="robots" content="nofollow" /><meta name="generator" content="FreeBSD-CVSweb 3.0.5" /><meta http-equiv="Content-Script-Type" content="text/javascript" /><meta http-equiv="Content-Style-Type" content="text/css" /><link rel="stylesheet" type="text/css" href="/css/cvsweb.css" /></head><body class="src"><table class="navigate-header" width="100%" summary="Navigation"> <tr> <td><a href="./pci_conf_cyc_addr_dec.v#rev1.1"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_conf_cyc_addr_dec.v#rev1.1">pci_conf_cyc_addr_dec.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td> <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td> </tr></table><hr /><div class="log-markup">File: <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_conf_cyc_addr_dec.v">pci_conf_cyc_addr_dec.v</a><br /><a name="rev1.1"></a><a name="wb2hpi"></a><a name="rel_WB_B3"></a><a name="rel_9"></a><a name="rel_8"></a><a name="rel_7"></a><a name="rel_6"></a><a name="rel_5"></a><a name="rel_4"></a><a name="rel_13"></a><a name="rel_12"></a><a name="rel_11"></a><a name="rel_10"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a><a name="MAIN"></a> Revision <b>1.1</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_conf_cyc_addr_dec.v?rev=1.1;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_conf_cyc_addr_dec.v?rev=1.1;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_conf_cyc_addr_dec.v?annotate=1.1">annotated</a> - <a href="pci_conf_cyc_addr_dec.v?r1=1.1#rev1.1">select for diffs</a><br /><i>Mon Jan 27 16:49:31 2003 UTC</i> (4 years, 3 months ago) by <i>mihad</i><br />Branches: <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=wb2hpi">wb2hpi</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_9">rel_9</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_8">rel_8</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_7">rel_7</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_6">rel_6</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_5">rel_5</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_4">rel_4</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_13">rel_13</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_12">rel_12</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_11">rel_11</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_10">rel_10</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=asyst_3">asyst_3</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=asyst_2">asyst_2</a>,<a href="./pci_conf_cyc_addr_dec.v?only_with_tag=HEAD">HEAD</a><br /><pre class="log">Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.</pre></div><hr /><pre>////////////////////////////////////////////////////////////////////////// //////// File name "conf_cyc_addr_dec.v" //////// //////// This file is part of the "PCI bridge" project //////// http://www.opencores.org/cores/pci/ //////// //////// Author(s): //////// - Miha Dolenc (mihad@opencores.org) //////// //////// All additional information is avaliable in the README //////// file. //////// //////// ////////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: pci_conf_cyc_addr_dec.v,v $// Revision 1.1 2003/01/27 16:49:31 mihad// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.//// Revision 1.3 2002/02/01 15:25:12 mihad// Repaired a few bugs, updated specification, added test bench files and design document//// Revision 1.2 2001/10/05 08:14:28 mihad// Updated all files with inclusion of timescale file for simulation purposes.//// Revision 1.1.1.1 2001/10/02 15:33:46 mihad// New project directory structure////// module is a simple decoder which decodes device num field of configuration address// for type0 configuration cycles. If type 1 configuration cycle is// initiated then address goes through unchanged// synopsys translate_off`include "timescale.v"// synopsys translate_onmodule pci_conf_cyc_addr_dec( ccyc_addr_in, ccyc_addr_out) ;input [31:0] ccyc_addr_in ;output [31:0] ccyc_addr_out ;reg [31:11] ccyc_addr_31_11 ;// lower 11 address lines are alweys going through unchangedassign ccyc_addr_out = {ccyc_addr_31_11, ccyc_addr_in[10:0]} ;// configuration cycle type indicatorwire ccyc_type = ccyc_addr_in[0] ;always@(ccyc_addr_in or ccyc_type)begin if (ccyc_type) // type 1 cycle - address goes through unchanged ccyc_addr_31_11 = ccyc_addr_in[31:11] ; else begin // type 0 conf. cycle - decode device number field to appropriate value case (ccyc_addr_in[15:11]) 5'h00:ccyc_addr_31_11 = 21'h00_0001 ; 5'h01:ccyc_addr_31_11 = 21'h00_0002 ; 5'h02:ccyc_addr_31_11 = 21'h00_0004 ; 5'h03:ccyc_addr_31_11 = 21'h00_0008 ; 5'h04:ccyc_addr_31_11 = 21'h00_0010 ; 5'h05:ccyc_addr_31_11 = 21'h00_0020 ; 5'h06:ccyc_addr_31_11 = 21'h00_0040 ; 5'h07:ccyc_addr_31_11 = 21'h00_0080 ; 5'h08:ccyc_addr_31_11 = 21'h00_0100 ; 5'h09:ccyc_addr_31_11 = 21'h00_0200 ; 5'h0A:ccyc_addr_31_11 = 21'h00_0400 ; 5'h0B:ccyc_addr_31_11 = 21'h00_0800 ; 5'h0C:ccyc_addr_31_11 = 21'h00_1000 ; 5'h0D:ccyc_addr_31_11 = 21'h00_2000 ; 5'h0E:ccyc_addr_31_11 = 21'h00_4000 ; 5'h0F:ccyc_addr_31_11 = 21'h00_8000 ; 5'h10:ccyc_addr_31_11 = 21'h01_0000 ; 5'h11:ccyc_addr_31_11 = 21'h02_0000 ; 5'h12:ccyc_addr_31_11 = 21'h04_0000 ; 5'h13:ccyc_addr_31_11 = 21'h08_0000 ; 5'h14:ccyc_addr_31_11 = 21'h10_0000 ; default: ccyc_addr_31_11 = 21'h00_0000 ; endcase endendendmodule</pre><hr /><address><span style="font-size: smaller">FreeBSD-CVSweb <<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>></span></address></body></html><!-- pf_body_end --></td><td><img width=15 src="/images/dotty.gif"></td></tr></table><xcenter><p><table width=100% cellpadding=0 cellspacing=0 border=0> <tr><td align=right valign=bottom><a title='Top' href='#top'><img border=0 alt='Top' src='/images/hr_up.gif'></a></td></tr> <tr><td background='/images/hpd.gif'><img height=1 border=0 src='/images/dotty.gif'></td></tr><tr><td height=4><img height=4 src='/images/dotty.gif'></td></tr></table> <br><!--<table border=0 cellpadding=0 cellspacing=1 bgcolor=#ffffff><tr><td><table cellpadding=0 cellspacing=0 border=0 bgcolor=#ffffff><tr><td>//--><script type="text/javascript"><!--google_ad_client = "pub-9285819221080148";google_alternate_color = "FFFFFF";google_ad_width = 728;google_ad_height = 90;google_ad_format = "728x90_as";google_ad_type = "text_image";google_ad_channel ="3034172958";google_color_border = "ffffff";google_color_bg = "ffffff";google_color_link = "444488";google_color_url = "b00000";google_color_text = "666666";//--></script><script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"></script><!--</td></tr></table></td></tr></table>//--></center><img border=0 src="/images/dotty.gif" height=1 width=400><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30></td></tr></table> </td></tr><tr bgcolor=#000000><td><img height=1 src="/images/dotty.gif"></td></tr></table><table background="/images/topbg.gif" width=100% cellpadding=0 cellspacing=0 border=0 bgcolor=#aaddff><tr><td align=right>Copyright (c) 1999-2007 OPENCORES.ORG. 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