📄 pci_cur_out_reg(1).v
字号:
</table></td><td width=10><img width=10 src="/images/dotty.gif"></td><td background="/images/vpd.gif"><img width=1 src="/images/dotty.gif"></td><td width=10><img width=10 src="/images/dotty.gif"></td><td valign=top> <table width=100% cellpadding=2 cellspacing=0 border=0> <tr><td><img height=2 src="/images/dotty.gif"></td></tr> </table> <table width=100% cellspacing=0 cellpadding=0 border=0><tr><td><!-- pf_body_start --> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html><head><title>pci/rtl/verilog/pci_cur_out_reg.v - view - 1.1</title><meta name="robots" content="nofollow" /><meta name="generator" content="FreeBSD-CVSweb 3.0.5" /><meta http-equiv="Content-Script-Type" content="text/javascript" /><meta http-equiv="Content-Style-Type" content="text/css" /><link rel="stylesheet" type="text/css" href="/css/cvsweb.css" /></head><body class="src"><table class="navigate-header" width="100%" summary="Navigation"> <tr> <td><a href="./pci_cur_out_reg.v#rev1.1"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_cur_out_reg.v#rev1.1">pci_cur_out_reg.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td> <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td> </tr></table><hr /><div class="log-markup">File: <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_cur_out_reg.v">pci_cur_out_reg.v</a><br /><a name="rev1.1"></a><a name="wb2hpi"></a><a name="rel_WB_B3"></a><a name="rel_9"></a><a name="rel_8"></a><a name="rel_7"></a><a name="rel_6"></a><a name="rel_5"></a><a name="rel_4"></a><a name="rel_13"></a><a name="rel_12"></a><a name="rel_11"></a><a name="rel_10"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a><a name="MAIN"></a> Revision <b>1.1</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_cur_out_reg.v?rev=1.1;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_cur_out_reg.v?rev=1.1;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_cur_out_reg.v?annotate=1.1">annotated</a> - <a href="pci_cur_out_reg.v?r1=1.1#rev1.1">select for diffs</a><br /><i>Mon Jan 27 16:49:31 2003 UTC</i> (4 years, 3 months ago) by <i>mihad</i><br />Branches: <a href="./pci_cur_out_reg.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./pci_cur_out_reg.v?only_with_tag=wb2hpi">wb2hpi</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_9">rel_9</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_8">rel_8</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_7">rel_7</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_6">rel_6</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_5">rel_5</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_4">rel_4</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_13">rel_13</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_12">rel_12</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_11">rel_11</a>,<a href="./pci_cur_out_reg.v?only_with_tag=rel_10">rel_10</a>,<a href="./pci_cur_out_reg.v?only_with_tag=asyst_3">asyst_3</a>,<a href="./pci_cur_out_reg.v?only_with_tag=asyst_2">asyst_2</a>,<a href="./pci_cur_out_reg.v?only_with_tag=HEAD">HEAD</a><br /><pre class="log">Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.</pre></div><hr /><pre>////////////////////////////////////////////////////////////////////////// //////// File name "cur_out_reg.v" //////// //////// This file is part of the "PCI bridge" project //////// http://www.opencores.org/cores/pci/ //////// //////// Author(s): //////// - Miha Dolenc (mihad@opencores.org) //////// //////// All additional information is avaliable in the README //////// file. //////// //////// ////////////////////////////////////////////////////////////////////////////// //////// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org //////// //////// This source file may be used and distributed without //////// restriction provided that this copyright statement is not //////// removed from the file and that any derivative work contains //////// the original copyright notice and the associated disclaimer. //////// //////// This source file is free software; you can redistribute it //////// and/or modify it under the terms of the GNU Lesser General //////// Public License as published by the Free Software Foundation; //////// either version 2.1 of the License, or (at your option) any //////// later version. //////// //////// This source is distributed in the hope that it will be //////// useful, but WITHOUT ANY WARRANTY; without even the implied //////// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //////// PURPOSE. See the GNU Lesser General Public License for more //////// details. //////// //////// You should have received a copy of the GNU Lesser General //////// Public License along with this source; if not, download it //////// from http://www.opencores.org/lgpl.shtml //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: pci_cur_out_reg.v,v $// Revision 1.1 2003/01/27 16:49:31 mihad// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.//// Revision 1.3 2002/02/01 15:25:12 mihad// Repaired a few bugs, updated specification, added test bench files and design document//// Revision 1.2 2001/10/05 08:14:28 mihad// Updated all files with inclusion of timescale file for simulation purposes.//// Revision 1.1.1.1 2001/10/02 15:33:46 mihad// New project directory structure////// synopsys translate_off`include "timescale.v"// synopsys translate_on`include "pci_constants.v"// module is only a backup copy of relevant output registers// used in some arhitectures that support IOB registers, which have to have a// fanout of 1// Otherwise nothing special in this modulemodule pci_cur_out_reg( reset_in, clk_in, frame_in, frame_load_in, irdy_in, devsel_in, trdy_in, trdy_en_in, stop_in, ad_load_in, cbe_in, cbe_en_in, mas_ad_in, tar_ad_in, frame_en_in, irdy_en_in, mas_ad_en_in, tar_ad_en_in, ad_en_unregistered_in, par_in, par_en_in, perr_in, perr_en_in, serr_in, serr_en_in, frame_out, irdy_out, devsel_out, trdy_out, stop_out, cbe_out, cbe_en_out, ad_out, frame_en_out, irdy_en_out, ad_en_out, mas_ad_en_out, tar_ad_en_out, trdy_en_out, par_out, par_en_out, perr_out, perr_en_out, serr_out, serr_en_out) ;input reset_in, clk_in ;input frame_in ;input frame_load_in ;input irdy_in ;input devsel_in ;input trdy_in ;input stop_in ;input ad_load_in ;input [3:0] cbe_in ;input cbe_en_in ;input [31:0] mas_ad_in ;input [31:0] tar_ad_in ;input mas_ad_en_in ;input tar_ad_en_in ;input ad_en_unregistered_in ;input frame_en_in, irdy_en_in ;input trdy_en_in ;input par_in ;input par_en_in ;input perr_in ;input perr_en_in ;input serr_in ;input serr_en_in ;output frame_out ;reg frame_out ;output irdy_out ;reg irdy_out ;output devsel_out ;reg devsel_out ;output trdy_out ;reg trdy_out ;output stop_out ;reg stop_out ;output [3:0] cbe_out ;reg [3:0] cbe_out ;output [31:0] ad_out ;reg [31:0] ad_out ;output frame_en_out, irdy_en_out, ad_en_out, cbe_en_out, mas_ad_en_out, tar_ad_en_out, trdy_en_out ;reg frame_en_out, irdy_en_out, cbe_en_out, mas_ad_en_out, tar_ad_en_out, trdy_en_out;output par_out ;output par_en_out ;output perr_out ;output perr_en_out ;output serr_out ;output serr_en_out ;reg par_out ;reg par_en_out ;reg perr_out ;reg perr_en_out ;reg serr_out ;reg serr_en_out ;assign ad_en_out = mas_ad_en_out || tar_ad_en_out ;always@(posedge reset_in or posedge clk_in)begin if ( reset_in ) begin irdy_out <= #`FF_DELAY 1'b1 ; devsel_out <= #`FF_DELAY 1'b1 ; trdy_out <= #`FF_DELAY 1'b1 ; stop_out <= #`FF_DELAY 1'b1 ; frame_en_out <= #`FF_DELAY 1'b0 ; irdy_en_out <= #`FF_DELAY 1'b0 ; mas_ad_en_out<= #`FF_DELAY 1'b0 ; tar_ad_en_out<= #`FF_DELAY 1'b0 ; trdy_en_out <= #`FF_DELAY 1'b0 ; par_out <= #`FF_DELAY 1'b0 ; par_en_out <= #`FF_DELAY 1'b0 ; perr_out <= #`FF_DELAY 1'b1 ; perr_en_out <= #`FF_DELAY 1'b0 ; serr_out <= #`FF_DELAY 1'b1 ; serr_en_out <= #`FF_DELAY 1'b0 ; cbe_en_out <= #`FF_DELAY 1'b0 ; end else begin irdy_out <= #`FF_DELAY irdy_in ; devsel_out <= #`FF_DELAY devsel_in ; trdy_out <= #`FF_DELAY trdy_in ; stop_out <= #`FF_DELAY stop_in ; frame_en_out <= #`FF_DELAY frame_en_in ; irdy_en_out <= #`FF_DELAY irdy_en_in ; mas_ad_en_out<= #`FF_DELAY mas_ad_en_in && ad_en_unregistered_in ; tar_ad_en_out<= #`FF_DELAY tar_ad_en_in && ad_en_unregistered_in ; trdy_en_out <= #`FF_DELAY trdy_en_in ; par_out <= #`FF_DELAY par_in ; par_en_out <= #`FF_DELAY par_en_in ; perr_out <= #`FF_DELAY perr_in ; perr_en_out <= #`FF_DELAY perr_en_in ; serr_out <= #`FF_DELAY serr_in ; serr_en_out <= #`FF_DELAY serr_en_in ; cbe_en_out <= #`FF_DELAY cbe_en_in ; endendalways@(posedge reset_in or posedge clk_in)begin if ( reset_in ) cbe_out <= #`FF_DELAY 4'hF ; else if ( ad_load_in ) cbe_out <= #`FF_DELAY cbe_in ;endwire [31:0] ad_source = tar_ad_en_out ? tar_ad_in : mas_ad_in ;always@(posedge reset_in or posedge clk_in)begin if ( reset_in ) ad_out <= #`FF_DELAY 32'h0000_0000 ; else if ( ad_load_in ) ad_out <= #`FF_DELAY ad_source ;endalways@(posedge reset_in or posedge clk_in)begin if ( reset_in ) frame_out <= #`FF_DELAY 1'b1 ; else if ( frame_load_in ) frame_out <= #`FF_DELAY frame_in ;endendmodule</pre><hr /><address><span style="font-size: smaller">FreeBSD-CVSweb <<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>></span></address></body></html><!-- pf_body_end --></td><td><img width=15 src="/images/dotty.gif"></td></tr></table><xcenter><p><table width=100% cellpadding=0 cellspacing=0 border=0> <tr><td align=right valign=bottom><a title='Top' href='#top'><img border=0 alt='Top' src='/images/hr_up.gif'></a></td></tr> <tr><td background='/images/hpd.gif'><img height=1 border=0 src='/images/dotty.gif'></td></tr><tr><td height=4><img height=4 src='/images/dotty.gif'></td></tr></table> <br><!--<table border=0 cellpadding=0 cellspacing=1 bgcolor=#ffffff><tr><td><table cellpadding=0 cellspacing=0 border=0 bgcolor=#ffffff><tr><td>//--><script type="text/javascript"><!--google_ad_client = "pub-9285819221080148";google_alternate_color = "FFFFFF";google_ad_width = 728;google_ad_height = 90;google_ad_format = "728x90_as";google_ad_type = "text_image";google_ad_channel ="3034172958";google_color_border = "ffffff";google_color_bg = "ffffff";google_color_link = "444488";google_color_url = "b00000";google_color_text = "666666";//--></script><script type="text/javascript" src="http://pagead2.googlesyndication.com/pagead/show_ads.js"></script><!--</td></tr></table></td></tr></table>//--></center><img border=0 src="/images/dotty.gif" height=1 width=400><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30><img border=0 src="/images/dotty.gif" height=1 width=30></td></tr></table> </td></tr><tr bgcolor=#000000><td><img height=1 src="/images/dotty.gif"></td></tr></table><table background="/images/topbg.gif" width=100% cellpadding=0 cellspacing=0 border=0 bgcolor=#aaddff><tr><td align=right>Copyright (c) 1999-2007 OPENCORES.ORG. All rights reserved. </td></tr><tr><td> </td></tr></table></td><td width=1 bgcolor=#000000><img width=1 src="/images/dotty.gif"></td><td width=1 bgcolor=#f0f0c8><img width=1 src="/images/dotty.gif"></td></tr></table></center><!-- pf_footer_start --> </body></html><!-- pf_footer_end -->⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -