📄 timescale(1).v
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<tr><td><img height=2 src="/images/dotty.gif"></td></tr> </table> <table width=100% cellspacing=0 cellpadding=0 border=0><tr><td><!-- pf_body_start --> <!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd"><html><head><title>pci/rtl/verilog/timescale.v - view - 1.2</title><meta name="robots" content="nofollow" /><meta name="generator" content="FreeBSD-CVSweb 3.0.5" /><meta http-equiv="Content-Script-Type" content="text/javascript" /><meta http-equiv="Content-Style-Type" content="text/css" /><link rel="stylesheet" type="text/css" href="/css/cvsweb.css" /></head><body class="src"><table class="navigate-header" width="100%" summary="Navigation"> <tr> <td><a href="./timescale.v#rev1.2"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./timescale.v#rev1.2">timescale.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td> <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td> </tr></table><hr /><div class="log-markup">File: <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/timescale.v">timescale.v</a><br /><a name="rev1.2"></a><a name="wb2hpi"></a><a name="rel_WB_B3"></a><a name="rel_9"></a><a name="rel_8"></a><a name="rel_7"></a><a name="rel_6"></a><a name="rel_5"></a><a name="rel_4"></a><a name="rel_3"></a><a name="rel_2"></a><a name="rel_13"></a><a name="rel_12"></a><a name="rel_11"></a><a name="rel_10"></a><a name="rel_1"></a><a name="rel_00"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a> Revision <b>1.2</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/timescale.v?rev=1.2;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="timescale.v?rev=1.2;content-type=text%2Fplain" class="display-link">text</a>, <a href="timescale.v?annotate=1.2">annotated</a> - <a href="timescale.v?r1=1.2#rev1.2">select for diffs</a><br /><i>Fri Feb 1 15:25:13 2002 UTC</i> (5 years, 3 months ago) by <i>mihad</i><br />Branches: <a href="./timescale.v?only_with_tag=MAIN">MAIN</a><br />CVS tags: <a href="./timescale.v?only_with_tag=wb2hpi">wb2hpi</a>,<a href="./timescale.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,<a href="./timescale.v?only_with_tag=rel_9">rel_9</a>,<a href="./timescale.v?only_with_tag=rel_8">rel_8</a>,<a href="./timescale.v?only_with_tag=rel_7">rel_7</a>,<a href="./timescale.v?only_with_tag=rel_6">rel_6</a>,<a href="./timescale.v?only_with_tag=rel_5">rel_5</a>,<a href="./timescale.v?only_with_tag=rel_4">rel_4</a>,<a href="./timescale.v?only_with_tag=rel_3">rel_3</a>,<a href="./timescale.v?only_with_tag=rel_2">rel_2</a>,<a href="./timescale.v?only_with_tag=rel_13">rel_13</a>,<a href="./timescale.v?only_with_tag=rel_12">rel_12</a>,<a href="./timescale.v?only_with_tag=rel_11">rel_11</a>,<a href="./timescale.v?only_with_tag=rel_10">rel_10</a>,<a href="./timescale.v?only_with_tag=rel_1">rel_1</a>,<a href="./timescale.v?only_with_tag=rel_00">rel_00</a>,<a href="./timescale.v?only_with_tag=asyst_3">asyst_3</a>,<a href="./timescale.v?only_with_tag=asyst_2">asyst_2</a>,<a href="./timescale.v?only_with_tag=HEAD">HEAD</a><br /><pre class="log">Repaired a few bugs, updated specification, added test bench files and design document</pre></div><hr /><pre>////////////////////////////////////////////////////////////////////////// //////// File name "timescale.v" //////// ////////////////////////////////////////////////////////////////////////////// CVS Revision History//// $Log: timescale.v,v $// Revision 1.2 2002/02/01 15:25:13 mihad// Repaired a few bugs, updated specification, added test bench files and design document//// Revision 1.1 2001/10/05 08:11:22 mihad// Updated all files with inclusion of timescale file for simulation purposes.////// timescale directive is included in all core's modules for simulation purposes`timescale 1ns/1ps</pre><hr /><address><span style="font-size: smaller">FreeBSD-CVSweb <<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>></span></address></body></html><!-- pf_body_end --></td><td><img width=15 src="/images/dotty.gif"></td></tr></table><xcenter><p><table width=100% cellpadding=0 cellspacing=0 border=0> <tr><td align=right valign=bottom><a title='Top' href='#top'><img border=0 alt='Top' src='/images/hr_up.gif'></a></td></tr> <tr><td background='/images/hpd.gif'><img height=1 border=0 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