pci_conf_space(1).v

PCI-master的核

-------------------------------------------------------------------------------------------------------------
General Interrupt registers
	There are also some registers with NOT all bits implemented and therefor uses _bitX or _bitX2_X1 to
	sign which bit or range of bits are implemented.
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------
[FF8h-FFCh]
	Bit 31 in the Interrupt Control register is set by software and used to generate SOFT RESET. Other 4
	bits are used to enable interrupt generations.
	5 LSbits in the Interrupt Status register are indicating System Error Int, Parity Error Int, PCI & WB
	Error Int and Inerrupt respecively. System and Parity errors are implented only in HOST bridge
	implementations!
-----------------------------------------------------------------------------------------------------------*/
			reg					icr_bit31 ;
`ifdef		HOST
			reg		[4 : 3]		icr_bit4_3              ;
			reg		[4 : 3]		isr_bit4_3              ;
			reg		[2 : 0]		icr_bit2_0              ;
			reg		[2 : 0]		isr_bit2_0              ;
`else // GUEST
			wire	[4 : 3]		icr_bit4_3 = 2'h0 ;
			wire	[4 : 3]		isr_bit4_3 = 2'h0 ;
			reg		[2 : 0]		icr_bit2_0 ;
			reg		[2 : 0]		isr_bit2_0 ;
`endif

/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
Initialization complete identifier
    When using I2C or similar initialisation mechanism,
    the bridge must not respond to transaction requests on PCI bus,
    not even to configuration cycles.
    Therefore, only when init_complete is set, the bridge starts
    participating on the PCI bus as an active device.
    Two additional flip flops are also provided for GUEST implementation,
    to synchronize to the pci clock after PCI reset is asynchronously de-asserted.
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

`ifdef GUEST

reg rst_inactive_sync ;
reg rst_inactive      ;

`else

wire rst_inactive = 1'b1 ;

`endif

reg init_complete   ;

wire    sync_init_complete ;

`ifdef HOST
assign  wb_init_complete_out = init_complete ;

pci_synchronizer_flop #(1, 0) i_pci_init_complete_sync
(
    .data_in        (   init_complete       ), 
    .clk_out        (   pci_clk             ), 
    .sync_data_out  (   sync_init_complete  ), 
    .async_reset    (   reset               )
);

reg pci_init_complete_out ;

always@(posedge pci_clk or posedge reset)
begin
    if (reset)
        pci_init_complete_out <= 1'b0 ;
    else
        pci_init_complete_out <= sync_init_complete ;
end

`endif

`ifdef GUEST

assign  pci_init_complete_out = init_complete ;

pci_synchronizer_flop #(1, 0) i_wb_init_complete_sync
(
    .data_in        (   init_complete       ), 
    .clk_out        (   wb_clk              ), 
    .sync_data_out  (   sync_init_complete  ), 
    .async_reset    (   reset               )
);

reg wb_init_complete_out ;

always@(posedge wb_clk or posedge reset)
begin
    if (reset)
        wb_init_complete_out <= 1'b0 ;
    else
        wb_init_complete_out <= sync_init_complete ;
end

`endif

/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------


-----------------------------------------------------------------------------------------------------------*/

`ifdef NO_CNF_IMAGE // if IMAGE0 is assigned as general image space

		assign	r_conf_data_out = 32'h0000_0000 ;

`else

    always@(r_conf_address_in or
    		status_bit15_11 or status_bit8 or r_status_bit4 or command_bit8 or command_bit6 or command_bit2_0 or
    		latency_timer or cache_line_size_reg or r_vendor_id or r_device_id or r_revision_id or
            r_subsys_vendor_id or r_subsys_id or r_max_lat or r_min_gnt or
    		pci_ba0_bit31_8 or
    		pci_img_ctrl0_bit2_1 or pci_am0 or pci_ta0 or pci_ba0_bit0 or
    		pci_img_ctrl1_bit2_1 or pci_am1 or pci_ta1 or pci_ba1_bit31_8  or pci_ba1_bit0 or
    		pci_img_ctrl2_bit2_1 or pci_am2 or pci_ta2 or pci_ba2_bit31_8 or pci_ba2_bit0 or
    		pci_img_ctrl3_bit2_1 or pci_am3 or pci_ta3 or pci_ba3_bit31_8 or pci_ba3_bit0 or
    		pci_img_ctrl4_bit2_1 or pci_am4 or pci_ta4 or pci_ba4_bit31_8 or pci_ba4_bit0 or
    		pci_img_ctrl5_bit2_1 or pci_am5 or pci_ta5 or pci_ba5_bit31_8 or pci_ba5_bit0 or
    		interrupt_line or
    		pci_err_cs_bit31_24 or pci_err_cs_bit10 or pci_err_cs_bit9 or pci_err_cs_bit8 or pci_err_cs_bit0 or
    		pci_err_addr or pci_err_data or
    		wb_ba0_bit31_12 or wb_ba0_bit0 or
    		wb_img_ctrl1_bit2_0 or wb_ba1_bit31_12 or wb_ba1_bit0 or wb_am1 or wb_ta1 or
    		wb_img_ctrl2_bit2_0 or wb_ba2_bit31_12 or wb_ba2_bit0 or wb_am2 or wb_ta2 or
    		wb_img_ctrl3_bit2_0 or wb_ba3_bit31_12 or wb_ba3_bit0 or wb_am3 or wb_ta3 or
    		wb_img_ctrl4_bit2_0 or wb_ba4_bit31_12 or wb_ba4_bit0 or wb_am4 or wb_ta4 or
    		wb_img_ctrl5_bit2_0 or wb_ba5_bit31_12 or wb_ba5_bit0 or wb_am5 or wb_ta5 or
    		wb_err_cs_bit31_24 or /*wb_err_cs_bit10 or*/ wb_err_cs_bit9 or wb_err_cs_bit8 or wb_err_cs_bit0 or
    		wb_err_addr or wb_err_data or
    		cnf_addr_bit23_2 or cnf_addr_bit0 or icr_bit31 or icr_bit4_3 or icr_bit2_0 or isr_bit4_3 or isr_bit2_0

        `ifdef PCI_CPCI_HS_IMPLEMENT
            or hs_ins or hs_ext or hs_pi or hs_loo or hs_eim or hs_cap_id
        `endif

        `ifdef PCI_SPOCI
            or spoci_cs_nack or spoci_cs_write or spoci_cs_read or spoci_cs_adr or spoci_cs_dat
        `endif
    		)
    begin
    	case (r_conf_address_in[9:2])
    	// PCI header - configuration space
    	8'h0: r_conf_data_out = { r_device_id, r_vendor_id } ;
    	8'h1: r_conf_data_out = { status_bit15_11, r_status_bit10_9, status_bit8, r_status_bit7, 1'h0, r_status_bit5, r_status_bit4, 
    								 4'h0, 7'h00, command_bit8, 1'h0, command_bit6, 3'h0, command_bit2_0 } ;
    	8'h2: r_conf_data_out = { r_class_code, r_revision_id } ;
    	8'h3: r_conf_data_out = { 8'h00, r_header_type, latency_timer, cache_line_size_reg } ;
    	8'h4: 
    	begin
        `ifdef HOST
            `ifdef NO_CNF_IMAGE
    		    r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															      pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		    r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		    r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
            `else
                r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ;
                r_conf_data_out[11: 0] = 12'h000 ;
            `endif
        `endif

        `ifdef GUEST
            r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ;
            r_conf_data_out[11: 0] = 12'h000 ;
        `endif
    	end
    	8'h5: 
    	begin
    		r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															 pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
    	end
    	8'h6: 
    	begin
    		r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															 pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
    	end
    	8'h7: 
    	begin
    		r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															 pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		r_conf_data_out[0] = pci_ba3_bit0 & pci_am3[31];
    	end
    	8'h8: 
    	begin
    		r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba4_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															 pci_am4[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		r_conf_data_out[0] = pci_ba4_bit0 & pci_am4[31];
    	end
    	8'h9: 
    	begin
    		r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba5_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															 pci_am5[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		r_conf_data_out[0] = pci_ba5_bit0 & pci_am5[31];
    	end
        8'hB:
        begin
            r_conf_data_out = {r_subsys_id, r_subsys_vendor_id} ;
        end
    `ifdef PCI_CPCI_HS_IMPLEMENT
        8'hD:
        begin
            r_conf_data_out = {24'h0000_00, `PCI_CAP_PTR_VAL} ;
        end
    `endif
    	8'hf: r_conf_data_out = { r_max_lat, r_min_gnt, r_interrupt_pin, interrupt_line } ;
    `ifdef PCI_CPCI_HS_IMPLEMENT
        (`PCI_CAP_PTR_VAL >> 2):
        begin
            r_conf_data_out  = {8'h00, hs_ins, hs_ext, hs_pi, hs_loo, 1'b0, hs_eim, 1'b0, 8'h00, hs_cap_id} ;
        end
    `endif
  		// PCI target - configuration space
    	{2'b01, `P_IMG_CTRL0_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl0_bit2_1, 1'h0 } ;
        {2'b01, `P_BA0_ADDR}	  : 
        begin
    	`ifdef HOST
            `ifdef NO_CNF_IMAGE
    		    r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba0_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															      pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		    r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		    r_conf_data_out[0] = pci_ba0_bit0 & pci_am0[31];
            `else
                r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ;
                r_conf_data_out[11: 0] = 12'h000 ;
            `endif
        `endif

        `ifdef GUEST
            r_conf_data_out[31:12] = pci_ba0_bit31_8[31:12] ;
            r_conf_data_out[11: 0] = 12'h000 ;
        `endif
    	end
        {2'b01, `P_AM0_ADDR}: 
    	begin
        `ifdef HOST
            `ifdef NO_CNF_IMAGE
           	    r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		    r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
            `else
                r_conf_data_out[31:12] = pci_am0[31:12] ;
                r_conf_data_out[11: 0] = 12'h000        ;
            `endif
        `endif

        `ifdef GUEST
            r_conf_data_out[31:12] = pci_am0[31:12] ;
            r_conf_data_out[11: 0] = 12'h000        ;
        `endif
    	end
        {2'b01, `P_TA0_ADDR}: 
    	begin
            r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta0[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
    	end
        {2'b01, `P_IMG_CTRL1_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl1_bit2_1, 1'h0 } ;
        {2'b01, `P_BA1_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba1_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    	 														  pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		r_conf_data_out[0] = pci_ba1_bit0 & pci_am1[31];
    	end
        {2'b01, `P_AM1_ADDR}: 
    	begin
           	r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
    	end
        {2'b01, `P_TA1_ADDR}: 
    	begin
           	r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta1[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
    	end
        {2'b01, `P_IMG_CTRL2_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl2_bit2_1, 1'h0 } ;
        {2'b01, `P_BA2_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba2_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															  pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		r_conf_data_out[0] = pci_ba2_bit0 & pci_am2[31];
    	end
        {2'b01, `P_AM2_ADDR}: 
    	begin
           	r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_am2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
    	end
        {2'b01, `P_TA2_ADDR}: 
    	begin
           	r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ta2[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):0] = 0 ;
    	end
        {2'b01, `P_IMG_CTRL3_ADDR}: r_conf_data_out = { 29'h00000000, pci_img_ctrl3_bit2_1, 1'h0 } ;
        {2'b01, `P_BA3_ADDR}: 
    	begin
    		r_conf_data_out[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] = pci_ba3_bit31_8[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] & 
    															  pci_am3[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] ;
    		r_conf_data_out[(31-`PCI_NUM_OF_DEC_ADDR_LINES):1] = 0 ;
    		r_conf_d