pci_conf_space(1).v

PCI-master的核

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on

/*-----------------------------------------------------------------------------------------------------------
	w_ prefix is a sign for Write (and read) side of Dual-Port registers
	r_ prefix is a sign for Read only side of Dual-Port registers
In the first line there are DATA and ADDRESS ports, in the second line there are write enable and read
enable signals with chip-select (conf_hit) for config. space.
In the third line there are output signlas from Command register of the PCI configuration header !!!
In the fourth line there are input signals to Status register of the PCI configuration header !!!
In the fifth line there is output from Latency Timer & r_Interrupt pin registers of the PCI conf. header !!!
Following are IMAGE specific registers, from which PCI_BASE_ADDR registers are the same as base address
registers from the PCI conf. header !!!
-----------------------------------------------------------------------------------------------------------*/
					// normal R/W address, data and control
module pci_conf_space 
                (	w_conf_address_in, w_conf_data_in, w_conf_data_out, r_conf_address_in, r_conf_data_out,
					w_we_i, w_re, r_re, w_byte_en_in, w_clock, reset, pci_clk, wb_clk,
					// outputs from command register of the PCI header
					serr_enable, perr_response, pci_master_enable, memory_space_enable, io_space_enable,
					// inputs to status register of the PCI header
					perr_in, serr_in, master_abort_recv, target_abort_recv, target_abort_set, master_data_par_err,
					// output from cache_line_size, latency timer and r_interrupt_pin register of the PCI header
					cache_line_size_to_pci, cache_line_size_to_wb, cache_lsize_not_zero_to_wb,
					latency_tim,
					// output from all pci IMAGE registers
					pci_base_addr0, pci_base_addr1, pci_base_addr2, pci_base_addr3, pci_base_addr4, pci_base_addr5,
					pci_memory_io0, pci_memory_io1, pci_memory_io2, pci_memory_io3, pci_memory_io4, pci_memory_io5,
					pci_addr_mask0, pci_addr_mask1, pci_addr_mask2, pci_addr_mask3, pci_addr_mask4, pci_addr_mask5,
					pci_tran_addr0, pci_tran_addr1, pci_tran_addr2, pci_tran_addr3, pci_tran_addr4, pci_tran_addr5,
					pci_img_ctrl0,  pci_img_ctrl1,  pci_img_ctrl2,  pci_img_ctrl3,  pci_img_ctrl4,  pci_img_ctrl5,
					// input to pci error control and status register, error address and error data registers
					pci_error_be, pci_error_bc, pci_error_rty_exp, pci_error_es, pci_error_sig, pci_error_addr,
					pci_error_data,
					// output from all wishbone IMAGE registers
					wb_base_addr0, wb_base_addr1, wb_base_addr2, wb_base_addr3, wb_base_addr4, wb_base_addr5,
					wb_memory_io0, wb_memory_io1, wb_memory_io2, wb_memory_io3, wb_memory_io4, wb_memory_io5,
					wb_addr_mask0, wb_addr_mask1, wb_addr_mask2, wb_addr_mask3, wb_addr_mask4, wb_addr_mask5,
					wb_tran_addr0, wb_tran_addr1, wb_tran_addr2, wb_tran_addr3, wb_tran_addr4, wb_tran_addr5,
					wb_img_ctrl0,  wb_img_ctrl1,  wb_img_ctrl2,  wb_img_ctrl3,  wb_img_ctrl4,  wb_img_ctrl5,
					// input to wb error control and status register, error address and error data registers
					wb_error_be, wb_error_bc, wb_error_rty_exp, wb_error_es, wb_error_sig, wb_error_addr, wb_error_data,
					// output from conf. cycle generation register (sddress), int. control register & interrupt output
					config_addr, icr_soft_res, int_out,
					// input to interrupt status register
					isr_sys_err_int, isr_par_err_int, isr_int_prop,

                    pci_init_complete_out, wb_init_complete_out

                `ifdef PCI_CPCI_HS_IMPLEMENT
                    ,
                    pci_cpci_hs_enum_oe_o, pci_cpci_hs_led_oe_o, pci_cpci_hs_es_i
                `endif

                `ifdef PCI_SPOCI
                    ,
                    spoci_scl_oe_o, spoci_sda_i, spoci_sda_oe_o
                `endif
                ) ;


/*###########################################################################################################
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
	Input and output ports
	======================
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
###########################################################################################################*/

// output data
output	[31 : 0]				w_conf_data_out ;
output	[31 : 0]				r_conf_data_out ;
reg		[31 : 0]				w_conf_data_out ;

`ifdef	NO_CNF_IMAGE
`else
reg		[31 : 0]				r_conf_data_out ;
`endif

// input data
input	[31 : 0]				w_conf_data_in ;
wire	[31 : 0]				w_conf_pdata_reduced ; // reduced data written into PCI image registers
wire	[31 : 0]				w_conf_wdata_reduced ; // reduced data written into WB  image registers
// input address
input	[11 : 0]				w_conf_address_in ;
input	[11 : 0]				r_conf_address_in ;
// input control signals
input							w_we_i ;
input							w_re   ;
input							r_re   ;
input	[3 : 0]					w_byte_en_in ;
input							w_clock ;
input							reset ;
input							pci_clk ;
input							wb_clk ;
// PCI header outputs from command register
output							serr_enable ;
output							perr_response ;
output							pci_master_enable ;
output							memory_space_enable ;
output							io_space_enable ;
// PCI header inputs to status register
input							perr_in ;
input							serr_in ;
input							master_abort_recv ;
input							target_abort_recv ;
input							target_abort_set ;
input							master_data_par_err ;
// PCI header output from cache_line_size, latency timer and interrupt pin
output	[7 : 0]					cache_line_size_to_pci ; // sinchronized to PCI clock
output	[7 : 0]					cache_line_size_to_wb ;  // sinchronized to WB clock
output							cache_lsize_not_zero_to_wb ; // used in WBU and PCIU
output	[7 : 0]					latency_tim ;
//output	[2 : 0]					int_pin ; // only 3 LSbits are important!
// PCI output from image registers
`ifdef GUEST
    output	[31:12] pci_base_addr0 ;
`endif

`ifdef HOST
    `ifdef NO_CNF_IMAGE
        output	[31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr0 ;
    `else
        output	[31:12] pci_base_addr0 ;
    `endif
`endif

output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr1 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr2 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr3 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr4 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_base_addr5 ;
output							pci_memory_io0 ;
output							pci_memory_io1 ;
output							pci_memory_io2 ;
output							pci_memory_io3 ;
output							pci_memory_io4 ;
output							pci_memory_io5 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask0 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask1 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask2 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask3 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask4 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_addr_mask5 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr0 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr1 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr2 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr3 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr4 ;
output  [31:(32-`PCI_NUM_OF_DEC_ADDR_LINES)] pci_tran_addr5 ;
output  [2 : 1]                 pci_img_ctrl0 ;
output  [2 : 1]                 pci_img_ctrl1 ;
output  [2 : 1]                 pci_img_ctrl2 ;
output  [2 : 1]                 pci_img_ctrl3 ;
output  [2 : 1]                 pci_img_ctrl4 ;
output  [2 : 1]                 pci_img_ctrl5 ;
// PCI input to pci error control and status register, error address and error data registers
input	[3 : 0]					pci_error_be ;
input   [3 : 0]                 pci_error_bc ;
input                           pci_error_rty_exp ;
input							pci_error_es ;
input                           pci_error_sig ;
input   [31 : 0]                pci_error_addr ;
input   [31 : 0]                pci_error_data ;
// WISHBONE output from image registers
output	[31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr0 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr1 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr2 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr3 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr4 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_base_addr5 ;
output							wb_memory_io0 ;
output							wb_memory_io1 ;
output							wb_memory_io2 ;
output							wb_memory_io3 ;
output							wb_memory_io4 ;
output							wb_memory_io5 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask0 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask1 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask2 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask3 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask4 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_addr_mask5 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr0 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr1 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr2 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr3 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr4 ;
output  [31:(32-`WB_NUM_OF_DEC_ADDR_LINES)] wb_tran_addr5 ;
output  [2 : 0]                 wb_img_ctrl0 ;
output  [2 : 0]                 wb_img_ctrl1 ;
output  [2 : 0]                 wb_img_ctrl2 ;
output  [2 : 0]                 wb_img_ctrl3 ;
output  [2 : 0]                 wb_img_ctrl4 ;
output  [2 : 0]                 wb_img_ctrl5 ;
// WISHBONE input to wb error control and status register, error address and error data registers
input	[3 : 0] 				wb_error_be ;
input   [3 : 0]	                wb_error_bc ;
input   		                wb_error_rty_exp ;
input                           wb_error_es ;
input                           wb_error_sig ;
input   [31 : 0]                wb_error_addr ;
input   [31 : 0]                wb_error_data ;
// GENERAL output from conf. cycle generation register & int. control register
output	[23 : 0]				config_addr ;
output                          icr_soft_res ;
output							int_out ;
// GENERAL input to interrupt status register
input                           isr_sys_err_int ;
input                           isr_par_err_int ;
input							isr_int_prop ;

output                          pci_init_complete_out ;
output                          wb_init_complete_out  ;

`ifdef PCI_CPCI_HS_IMPLEMENT
output  pci_cpci_hs_enum_oe_o   ; 
output  pci_cpci_hs_led_oe_o    ; 
input   pci_cpci_hs_es_i        ;

reg pci_cpci_hs_enum_oe_o   ; 
reg pci_cpci_hs_led_oe_o    ; 

// set the hot swap ejector switch debounce counter width
// it is only 4 for simulation purposes
`ifdef PCI_CPCI_SIM

    parameter hs_es_cnt_width = 4  ;

`else

    `ifdef PCI33
    
    parameter hs_es_cnt_width = 16 ;
    
    `endif
    
    `ifdef PCI66
    
    parameter hs_es_cnt_width = 17 ;
    
    `endif
`endif

`endif

`ifdef PCI_SPOCI
output  spoci_scl_oe_o  ;
input   spoci_sda_i     ;
output  spoci_sda_oe_o  ;

reg spoci_cs_nack,
    spoci_cs_write,
    spoci_cs_read;

reg [10: 0] spoci_cs_adr   ; 
reg [ 7: 0] spoci_cs_dat   ;
`endif

/*###########################################################################################################
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
	REGISTERS definition
	====================
/////////////////////////////////////////////////////////////////////////////////////////////////////////////
###########################################################################################################*/

// Decoded Register Select signals for writting (only one address decoder)
reg		[56 : 0]				w_reg_select_dec ;

/*###########################################################################################################
-------------------------------------------------------------------------------------------------------------
PCI CONFIGURATION SPACE HEADER (type 00h) registers

	BIST and some other registers are not implemented and therefor written in correct
	place with comment line. There are also some registers with NOT all bits implemented and therefor uses
	_bitX or _bitX2_X1 to sign which bit or range of bits are implemented.
	Some special cases and examples are described below!
-------------------------------------------------------------------------------------------------------------
###########################################################################################################*/

/*-----------------------------------------------------------------------------------------------------------
[000h-00Ch] First 4 DWORDs (32-bit) of PCI configuration header - the same regardless of the HEADER type !
			r_ prefix is a sign for read only registers
	Vendor_ID is an ID for a specific vendor defined by PCI_SIG - 2321h does not belong to anyone (e.g.
	Xilinx's Vendor_ID is 10EEh and Altera's Vendor_ID is 1172h). Device_ID and Revision_ID should be used
	together by application. Class_Code has 3 bytes to define BASE class (06h for PCI Bridge), SUB class
	(00h for HOST type, 80h for Other Bridge type) and Interface type (00h for normal).
-----------------------------------------------------------------------------------------------------------*/
            reg [15: 0] r_vendor_id         ;
            reg [15: 0] r_device_id         ;
            reg [15: 0] r_subsys_vendor_id  ;
            reg [15: 0] r_subsys_id         ;

			reg					command_bit8 ;
			reg					command_bit6 ;
			reg		[2 : 0]		command_bit2_0 ;
			reg		[15 : 11]	status_bit15_11 ;
			parameter			r_status_bit10_9 = 2'b01 ;	// 2'b01 means MEDIUM devsel timing !!!
			reg					status_bit8 ;
			parameter			r_status_bit7 = 1'b1 ; // fast back-to-back capable response !!!
			parameter			r_status_bit5 = `HEADER_66MHz ;   	// 1'b0 indicates 33 MHz capable !!!

`ifdef PCI_CPCI_HS_IMPLEMENT
            wire                r_status_bit4 = 1   ;
            reg                 hs_ins              ;
            reg                 hs_ext              ;
            wire    [ 1: 0]     hs_pi = 2'b00       ;
            reg                 hs_loo              ;
            reg                 hs_eim              ;
            wire    [ 7: 0]     hs_cap_id = 8'h06   ;
            reg                 hs_ins_armed        ;
            reg                 hs_ext_armed        ;
`else
            wire                r_status_bit4 = 0 ;
`endif