da5614.vhd

DAC5614的VHDL控制程序。通过四个地址可实现四路的D/A输出。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity da5614 is
port(
	clk		:	in	std_logic;
	eq_i	:	in	std_logic;
	ad_104	:	in	std_logic_vector(4 downto 0);
	d_104	:	inout	std_logic_vector(15 downto 0);
	siow	:	in	std_logic;
	sior	:	in	std_logic;
	--5614 signals
	sclk	:	out	std_logic;
	din		:	out	std_logic;
	da_cs	:	out	std_logic;
	fs		:	out	std_logic
);
end da5614;

architecture da5614s of da5614 is
signal  eq		:	std_logic;
signal	da_data	:	std_logic_vector(15 downto 0);
signal  da_data_t:	std_logic_vector(15 downto 0);
signal  da_data_tt:	std_logic_vector(11 downto 0);
signal	addr	:	std_logic_vector(3	downto 0);
signal  sclk_t	:	std_logic;
signal	fs_t	:	std_logic;
signal 	sclk_m	:	std_logic;
signal  da_con	:	std_logic;								--D/A convert start
signal	da_addr	:	std_logic_vector(7 downto 0);
signal	da_dat	:	std_logic_vector(7 downto 0);
begin
	eq<= not (eq or ad_104(4));
	addr<=ad_104(3 downto 0);
	da_con<= siow or (not (eq and addr(3) and (not addr(0))));
	da_data_tt<=d_104(11 downto 0);
	process(siow,addr,eq)
	begin
		if siow'event and siow='0' then
			if (eq='1' and addr="1000") then
				da_data<="0001"&da_data_tt;
			elsif (eq='1' and addr="1010") then
				da_data<="0101"&da_data_tt;
			elsif (eq='1' and addr="1100") then
				da_data<="1001"&da_data_tt;
			elsif (eq='1' and addr="1110") then
				da_data<="1101"&da_data_tt;
			else
				da_data<=da_data;
			end if;
		end if;
	end process;
	
	da_cs<='0';
	process(clk)
	variable	cnt_clk	:	std_logic_vector(10 downto 0);
	begin
		if clk'event and clk='1' then
			cnt_clk:=cnt_clk+1;
		end if;
		sclk_t<=cnt_clk(1);
	end process;
	sclk<=sclk_t;
	
	process(clk)
	begin
		if clk'event and clk='1' then
			sclk_m<=sclk_t;
		end if;	
	end process;
	
	process(sclk_t,da_con)
	variable	cnt_fs	:	integer range 0 to 20;
	begin
		if da_con='0' then
			cnt_fs:=0;
		elsif sclk_t'event and sclk_t='1' then
--		if sclk_t'event and sclk_t='1' then
			if	cnt_fs=20 then
				cnt_fs:=20;
			else
				cnt_fs:=cnt_fs+1;
			end if;
			if	((cnt_fs<2) or (cnt_fs=20)) then
				fs_t<='1';
			else
				fs_t<='0';
			end if;
		end if;
	end process;
	fs<=fs_t;
	
	process(fs_t)
	begin
		if fs_t'event and fs_t='1' then
			da_data_t<=da_data_t+1;
		end if;
--	da_data_tt<=da_data_t(13 downto 12)&"00"&da_data_t(11 downto 0);
	end process;

	
	process(sclk_m,fs_t)
	variable	i	:	integer range 0 to 19;
	begin
		if fs_t='1' then
			i:=15;
		elsif sclk_m'event and sclk_m='1' then
			if i>15 then
				din<='0'; 
			else
				din<=da_data(i);
				i:=i-1;
			end if;
		end if;
			
	end process;
	
end da5614s;