ads8361.vhd

TI公司的AD8361的VHDL控制程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ads8361 is
port(
	clk		:	in	std_logic;
	din		:	in	std_logic;
	ser_clk	:	out	std_logic;
	clk_en	:	out	std_logic;
	con_en	:	out	std_logic;
	con_end	:	out	std_logic;
	addata	:	out	std_logic_vector(15 downto 0)
);
end ads8361;

architecture ads8361s of ads8361 is
signal 	temp:	std_logic_vector(17 downto 0);
signal 	clk_n:	std_logic;
signal	con_temp:	std_logic;
begin
	process(clk)
	variable	cnt	:	std_logic_vector(10 downto 0);	
	begin
		if clk'event and clk='1' then
			cnt:=cnt+1;
		end if;
		clk_n<=cnt(2);
	end process;
	ser_clk<=clk_n;
	
	process(clk_n)
	variable	cnt2 :	std_logic_vector(4 downto 0);
	begin
		if clk_n'event and clk_n='1' then
			if	cnt2<20 then
				cnt2:=cnt2+1;
			else
				cnt2:="00000";
			end if;
			if	(cnt2=0 or cnt2=1) then
				con_temp<='1';
			else
				con_temp<='0';
			end if;
		end if;
	end process;
	con_en<=con_temp;
	
	process(clk_n,con_temp)
		variable	i	:	integer range 0 to 20;
	begin
		if con_temp='1' then
			temp<=(others=>'0');
			i:=17;
			con_end<='1';
		elsif clk_n'event and clk_n='1' then
			con_end<='0';
			temp(i)<=din;
			i:=i-1;
			if i<1 then
				addata<=temp(17 downto 2);
			end if;
		end if;
	end process;
end ads8361s;