ramchoice.vhd

多总线切换的VHDL代码。可用于多RAM的管理。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity ramchoice is
	generic(width: integer :=8;									--wide of data
			addth: integer :=15									--wide of address
			);
port(
	temp	:	out	std_logic;
	eq		:	in	std_logic;
	Rom_cs	:	in	std_logic;
	di		:	in	std_logic_vector(width-1 downto 0);
	do		:	out	std_logic_vector(width-1 downto 0);
	at		:	in	std_logic_vector(addth-1 downto 0);
	rd,wr	:	in	std_logic;									--MCU  bus
	
	ram_cs	:	in	std_logic;
	datao	:	out	std_logic_vector(width-1 downto 0);
	read	:	in	std_logic;
	write	:	in	std_logic;
	addrr	:	in	std_logic_vector(addth-1 downto 0);			--scan bus
	
	Ram1_cs	:	out	std_logic;
	ram1di	:	in	std_logic_vector(width-1 downto 0);
	ram1do	:	out	std_logic_vector(width-1 downto 0);
	ram1a	:	out	std_logic_vector(addth-1 downto 0);
	ram1_oe	:	out	std_logic;		
	rd1,wr1	:	out	std_logic;									--RAM1 bus
	
	Ram2_cs	:	out	std_logic;
	ram2di	:	in	std_logic_vector(width-1 downto 0);
	ram2do	:	out	std_logic_vector(width-1 downto 0);
	ram2a	:	out	std_logic_vector(addth-1 downto 0);			
	ram2_oe	:	out	std_logic;
	rd2,wr2	:	out	std_logic									--RAM2 bus
	);
end ramchoice;

architecture a of ramchoice is
signal cnt	:	std_logic_vector(1 downto 0) :="00";
--signal 	rams	:	std_logic;	
--signal cs688	:	std_logic;
begin

	--process(ale)
	--begin
		--if ale'event and ale='0' then
			--rams<=not(Rom_cs and at(0)and at(1)and at(2)and at(3)and at(4)and at(5)and at(6)and at(7)and at(8)and at(9)and at(10)and at(11)and at(12)and at(13)and at(14));
			--rams<=not((not Rom_cs)or(not at(0))or(not at(1))or(not at(2))or(not at(3))or(not at(4))or(not at(5))or(not at(6))or(not at(7))or(not at(8))or(not at(9))or(not at(10))or(not at(11))or(not at(12))or(not at(13))or(not at(14)));
		--end if;
	--end process;	
	
	--temp<=rams;
	--cs688<=wr and rd;
	
	process(eq)
	begin
		if (eq'event and eq='1') then
			cnt<=cnt+1;
		else
			cnt<=cnt;	
		end if;	
	end process;

	process(cnt,wr,rd)
	begin
		if	cnt(0)='1' and Rom_cs='1' then
			Ram1_cs<='0';
			do<=ram1di;
			ram1do<=di;
			ram1a<=at;
			rd1<=rd;
			wr1<=wr;
			ram1_oe<=(not rd);
			
			Ram2_cs<=ram_cs;
			datao<=ram2di;
			ram2do<=(others=>'Z');
			ram2a<=addrr;
			rd2<=read;
			wr2<=write;
			ram2_oe<='1';
		elsif	cnt(0)='0' and Rom_cs='1' then	
		--	Ram2_cs<=(not Rom_cs);
			Ram2_cs<='0';
			do<=ram2di;
			ram2do<=di;
			ram2a<=at;
			rd2<=rd;
			wr2<=wr;
			ram2_oe<=(not rd);
			
			Ram1_cs<=ram_cs;
			datao<=ram1di;
			ram1do<=(others=>'Z');
			ram1a<=addrr;
			rd1<=read;
			wr1<=write;
			ram1_oe<='1';
		else
			Ram2_cs<='1';
			ram2do<=(others=>'Z');
			do<=(others=>'Z');
			ram2a<=at;
			rd2<='1';
			wr2<='1';
			ram2_oe<='1';
			
			Ram1_cs<='1';
			ram1do<=(others=>'Z');
			ram1a<=(others=>'0');
			rd1<='1';
			wr1<='1';
			ram1_oe<='1';	
		end if;	
	end process;
	
end a;