📄 r40008.inc
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#------------------------------------------------------------------------------
#- ATMEL Microcontroller Software Support - ROUSSET -
#------------------------------------------------------------------------------
# The software is delivered "AS IS" without warranty or condition of any
# kind, either express, implied or statutory. This includes without
# limitation any warranty or condition with respect to merchantability or
# fitness for any particular purpose, or against the infringements of
# intellectual property rights of others.
#------------------------------------------------------------------------------
#- File Name : r40008.inc
#- Object : AT91R40008 Definition File.
#-
#- 1.0 06/08/01 PFi : Creation
#- 1.0 08/11/01 PFi : SRAM_LIMIT Definition has been modify
#------------------------------------------------------------------------------
#--------------------------------------
#- Peripheral Identifier and Interrupt
#--------------------------------------
.EQU FIQ_ID, 0 @- Fast Interrupt
.EQU SWIRQ_ID, 1 @- Soft Interrupt (generated by the AIC)
.EQU US0_ID, 2 @- USART Channel 0 interrupt
.EQU US1_ID, 3 @- USART Channel 1 interrupt
.EQU TC0_ID, 4 @- Timer Channel 0 interrupt
.EQU TC1_ID, 5 @- Timer Channel 1 interrupt
.EQU TC2_ID, 6 @- Timer Channel 2 interrupt
.EQU WDI_ID, 7 @- Watchdog interrupt
.EQU PIO_ID, 8 @- Parallel I/O Controller A interrupt
.EQU IRQ0_ID, 16 @- External interrupt 0
.EQU IRQ1_ID, 17 @- External interrupt 1
.EQU IRQ2_ID, 18 @- External interrupt 2
#------------------------
#- Peripheral Memory Map
#------------------------
.EQU WD_BASE, 0xFFFF8000 @- WD: Watchdog Timer Base Address
.EQU PIO_BASE, 0xFFFF0000 @- Parallel I/O Controller Base Address
.EQU USART1_BASE, 0xFFFCC000 @- USART 1 Base Address
.EQU USART0_BASE, 0xFFFD0000 @- USART 0 Base Address
#- Timer Counter Base Addresses
.EQU TCB0_BASE, 0xFFFE0000
.EQU TC0_BASE, 0xFFFE0000
.EQU TC1_BASE, 0xFFFE0040
.EQU TC2_BASE, 0xFFFE0080
#--------------------------
#- Internal RAM Definition
#--------------------------
# The Internal SRAM is redefined in two blocks (248K + 8K) due to the EB40A has no External SRAM.
# The 8K (from 0x0 to 0x01FFF) are for Vector table and Exception stack defined by RAM_LIMIT.
# The 248K (from 0x2000 to 0x3FFFF) are for User Application code and Application stack defined by EXT_SRAM_LIMIT
.EQU RAM_BASE, (0x00000000) @- Address of the Internal SRAM after the remap command
.EQU RAM_SIZE, (256*1024)
# **************
# * WARNING !!!* The RAM_LIMIT definition does not correspond to ( RAM_BASE + RAM_SIZE )
# **************
# - This is for compatipility with the cstartup_xxx.ads (flash, ice or angel).
.EQU RAM_LIMIT, (RAM_BASE + (8*1024)) @ The size of the Application stack is 8K.
#- The internal RAM is mapped at address 0x00300000 after reset until
#- Remap command is performed on the EBI.
.EQU RAM_BASE_BOOT, 0x00300000
#-----------
#- ARM Core
#-----------
.INCLUDE "../../periph/arm7tdmi/arm.inc"
#-----------------------------
#- Special Function Registers
#-----------------------------
.INCLUDE "../../periph/special_function/sf.inc"
#-------------------------
#- External Bus Interface
#-------------------------
.INCLUDE "../../periph/ebi/ebi.inc"
#---------------------------
#- Power Saving Controller
#---------------------------
.INCLUDE "../../periph/power_saving/ps40800.inc"
#--------------------------------
#- Advanced Interrupt Controller
#--------------------------------
.INCLUDE "../../periph/aic/aic.inc"
#--------------------------
#- Parallel I/O Controller
#--------------------------
.INCLUDE "../../periph/pio/pio.inc"
.INCLUDE "../../periph/pio/pio_single.inc"
.EQU NB_PIO, 31 @- Number of PIO Lines
#-------------------
#- Pin Multiplexing
#-------------------
#- PIO Controller
.EQU PIOTCLK0, 0 @- Timer 0 Clock signal
.EQU PIOTIOA0, 1 @- Timer 0 Signal A
.EQU PIOTIOB0, 2 @- Timer 0 Signal B
.EQU PIOTCLK1, 3 @- Timer 1 Clock signal
.EQU PIOTIOA1, 4 @- Timer 1 Signal A
.EQU PIOTIOB1, 5 @- Timer 1 Signal B
.EQU PIOTCLK2, 6 @- Timer 2 Clock signal input
.EQU PIOTIOA2, 7 @- Timer 2 Signal A
.EQU PIOTIOB2, 8 @- Timer 2 Signal B
.EQU PIOIRQ0, 9 @- External Interrupt 0
.EQU PIOIRQ1, 10 @- External Interrupt 1
.EQU PIOIRQ2, 11 @- External Interrupt 2
.EQU PIOFIQ, 12 @- Fast Interrupt input
.EQU PIOSCK0, 13 @- USART 0 clock signal
.EQU PIOTXD0, 14 @- USART 0 transmit data signal
.EQU PIORXD0, 15 @- USART 0 receive data signal
.EQU PIOSCK1, 20 @- USART 1 clock signal
.EQU PIOTXD1, 21 @- USART 1 transmit data signal
.EQU PIORXD1, 22 @- USART 1 receive data signal
.EQU PIOMCK0, 25 @- Master Clock Output
.EQU PIONCS2, 26 @- Chip Select 2
.EQU PIONCS3, 27 @- Chip Select 3
.EQU PIOCS7, 28 @- Address 20/Chip Select 7
.EQU PIOCS6, 29 @- Address 21/Chip Select 6
.EQU PIOCS5, 30 @- Address 22/Chip Select 5
.EQU PIOCS4, 31 @- Address 23/Chip Select 4
#---------
#- USARTs
#---------
#- Definition file
.INCLUDE "../../periph/usart/usart.inc"
#-----------
#- Watchdog
#-----------
#- Definition file
.INCLUDE "../../periph/watchdog/wd.inc"
#----------------
#- Timer Counter
#----------------
.INCLUDE "../../periph/timer_counter/tc.inc"
# .END
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