m63200.inc

ATMEL公司的arm7处理器AT91R4008的库函数,我之前做的一个项目里面使用到的,在此网站上发现没有类似的资料,贡献给大家,能用到的最好.

#------------------------------------------------------------------------------
#-         ATMEL Microcontroller Software Support  -  ROUSSET  -
#------------------------------------------------------------------------------
# The software is delivered "AS IS" without warranty or condition of any
# kind, either express, implied or statutory. This includes without
# limitation any warranty or condition with respect to merchantability or
# fitness for any particular purpose, or against the infringements of
# intellectual property rights of others.
#------------------------------------------------------------------------------
#- File Name            : m63200.inc
#- Object               : AT91M63200 Definition File.
#-
#- 1.0 01/04/00 JCZ     : Creation
#- 1.1 02/11/00 JPP     : Green Hills
#------------------------------------------------------------------------------

#------------------------
#- Peripheral Memory Map
#------------------------
# AIC, PMC, SF and EBI base addresses are described in periph header files.

.equ	WD_BASE,         0xFFFF8000      /* WD: Watchdog Timer 			*/
.equ	PIOB_BASE,       0xFFFF0000      /* Parallel I/O Controller B 	*/
.equ	PIOA_BASE,       0xFFFEC000      /* Parallel I/O Controller A 	*/
.equ	TCB1_BASE,       0xFFFD4000      /* Channels 3, 4, 5 			*/
.equ	TCB0_BASE,       0xFFFD0000      /* Channels 0, 1, 2 			*/
.equ	USART2_BASE,     0xFFFC8000      /* USART 2 					*/
.equ	USART1_BASE,     0xFFFC4000      /* USART 1 					*/
.equ	USART0_BASE,     0xFFFC0000      /* USART 0	 					*/
.equ	SPI_BASE,        0xFFFBC000      /* SPI 						*/

#----------------------------------
# Internal Memory Mapping and Size
#----------------------------------
 
.equ	RAM_BASE,        0
.equ	RAM_SIZE,        (2*1024)
.equ	RAM_LIMIT,       (RAM_BASE+RAM_SIZE)
.equ	RAM_BASE_BOOT,   0x00300000

#---------------------
# ARM Core : ARM7TDMI
#---------------------
        .INCLUDE         "../../periph/arm7tdmi/arm.inc"

#-----------------------------
#- Special Function Registers
#-----------------------------
        .INCLUDE         "../../periph/special_function/sf.inc"

#------------------------
# External Bus Interface
#------------------------
        .INCLUDE         "../../periph/ebi/ebi.inc"

#-----------------------------
# Power Management Controller
#-----------------------------
        .INCLUDE         "../../periph/power_saving/pmc63200.inc"

#-------------------------------------------------
# AIC Interrupt Sources and peripheral Identifier
#-------------------------------------------------
        .INCLUDE         "../../periph/aic/aic.inc"

.equ	AIC_FIQ_ID,      0       /* Fast Interrupt */
.equ	AIC_SWIRQ_ID,    1       /* Soft Interrupt (generated by the AIC) */
.equ	AIC_US0IRQ_ID,   2       /* USART Channel 0 interrupt */
.equ	AIC_US1IRQ_ID,   3       /* USART Channel 1 interrupt */
.equ	AIC_US2IRQ_ID,   4       /* USART Channel 2 interrupt */
.equ	AIC_SPIRQ_ID,    5       /* SPI interrupt */
.equ	AIC_TC0IRQ_ID,   6       /* Timer Channel 0 interrupt */
.equ	AIC_TC1IRQ_ID,   7       /* Timer Channel 1 interrupt */
.equ	AIC_TC2IRQ_ID,   8       /* Timer Channel 2 interrupt */
.equ	AIC_TC3IRQ_ID,   9       /* Timer Channel 3 interrupt */
.equ	AIC_TC4IRQ_ID,   10      /* Timer Channel 4 interrupt */
.equ	AIC_TC5IRQ_ID,   11      /* Timer Channel 5 interrupt */
.equ	AIC_WDIRQ_ID,    12      /* Watchdog interrupt */
.equ	AIC_PIOAIRQ_ID,  13      /* Parallel I/O Controller A interrupt */
.equ	AIC_PIOBIRQ_ID,  14      /* Parallel I/O Controller B interrupt */

.equ	AIC_IRQ3_ID,     28      /* External interrupt 3 */
.equ	AIC_IRQ2_ID,     29      /* External interrupt 2 */
.equ	AIC_IRQ1_ID,     30      /* External interrupt 1 */
.equ	AIC_IRQ0_ID,     31      /* External interrupt 0 */


#-----------------
# PIO Controllers
#-----------------
        .INCLUDE     "../../periph/pio/pioa.inc"
        .INCLUDE     "../../periph/pio/piob.inc"

.equ	NB_PIOA,         30      /* Number of PIO A Lines */
.equ	NB_PIOB,         28      /* Number of PIO A Lines */

# Port A

.equ	TCLK3,           PA0
.equ	TIOA3,           PA1
.equ	TIOB3,           PA2
.equ	PIN_TC3,         (TIOA3 | TIOB3 | TCLK3)

.equ	TCLK4,           PA3
.equ	TIOA4,           PA4
.equ	TIOB4,           PA5
.equ	PIN_TC4,         (TIOA4 | TIOB4 | TCLK4)

.equ	TCLK5,           PA6
.equ	TIOA5,           PA7
.equ	TIOB5,           PA8
.equ	PIN_TC5,         (TIOA5 | TIOB5 | TCLK5)

.equ	PIN_IRQ0,        PA9
.equ	PIN_IRQ1,        PA10
.equ	PIN_IRQ2,        PA11
.equ	PIN_IRQ3,        PA12
.equ	PIN_FIQ,         PA13

.equ	SCK0,            PA14
.equ	TXD0,            PA15
.equ	RXD0,            PA16
.equ	PIN_USART0,      (SCK0 | TXD0 | RXD0)

.equ	SCK1,            PA17
.equ	TXD1,            PA18
.equ	RXD1,            PA19
.equ	PIN_USART1,      (SCK1 | TXD1 | RXD1)

.equ	SCK2,            PA20
.equ	TXD2,            PA21
.equ	RXD2,            PA22
.equ	PIN_USART2,      (SCK2 | TXD2 | RXD2)

.equ	SPCK,            PA23
.equ	MISO,            PA24
.equ	MOSI,            PA25
.equ	NPCS0,           PA26
.equ	NPCS1,           PA27
.equ	NPCS2,           PA28
.equ	NPCS3,           PA29

# Port B

.equ	TCLK0,           PB19
.equ	TIOA0,           PB20
.equ	TIOB0,           PB21
.equ	PIN_TC0,         (TIOA0 | TIOB0 | TCLK0)

.equ	TCLK1,           PB22
.equ	TIOA1,           PB23
.equ	TIOB1,           PB24
.equ	PIN_TC1,         (TIOA1 | TIOB1 | TCLK1)

.equ	TCLK2,           PB25
.equ	TIOA2,           PB26
.equ	TIOB2,           PB27
.equ	PIN_TC2,         (TIOA2 | TIOB2 | TCLK2)

.equ	MCKO,            PB17

.equ	BMS,             PB18

.equ	MPI_NOE,         PB0
.equ	MPI_NLB,         PB1
.equ	MPI_NUB,         PB2

#                END