aic.inc

ATMEL公司的arm7处理器AT91R4008的库函数,我之前做的一个项目里面使用到的,在此网站上发现没有类似的资料,贡献给大家,能用到的最好.

#------------------------------------------------------------------------------
#-         ATMEL Microcontroller Software Support  -  ROUSSET  -
#------------------------------------------------------------------------------
# The software is delivered "AS IS" without warranty or condition of any
# kind, either express, implied or statutory. This includes without
# limitation any warranty or condition with respect to merchantability or
# fitness for any particular purpose, or against the infringements of
# intellectual property rights of others.
#------------------------------------------------------------------------------
#- File Name            : aic.inc
#- Object               : Assembler Advanced Interrupt Controller Definition File.
#-
#- 1.0 01/04/00 JCZ     : Creation
#- 1.1 15/11/00 JPP     : Update AIC values
#------------------------------------------------------------------------------

#------------------------------------------
#- AIC User Interface Structure Definition
#------------------------------------------

.equ			AIC_SMR,		0x000				/* Source Mode Register */
.equ			AIC_SVR,		0x080				/* Source Vector Register */
.equ			AIC_IVR,		0x100				/* Interrupt Vector Register */
.equ			AIC_FVR,		0x104				/* Fast Interrupt Vector Register */
.equ			AIC_ISR,		0x108				/* Interrupt Status Register */
.equ			AIC_IPR,		0x10c				/* Interrupt Pending Register */
.equ			AIC_IMR,		0x110				/* Interrupt Mask Register */
.equ			AIC_CISR,		0x114				/* Core Interrupt Status Register */
#;								0x118				/* Reserved 0 */
#;								0x11C				/* Reserved 1 */
.equ			AIC_IECR,		0x120           	/* Interrupt Enable Command Register */
.equ			AIC_IDCR,		0x124           	/* Interrupt Disable Command Register */
.equ			AIC_ICCR,		0x128           	/* Interrupt Clear Command Register */
.equ			AIC_ISCR,		0x12c           	/* Interrupt Set Command Register */
.equ			AIC_EOICR,		0x130	          	/* End Of Interrupt Command Register */
.equ			AIC_SPU,		0x134	          	/* Spurious Vector Register */

#---------------------------------------------
#- AIC_SMR[]: Interrupt Source Mode Registers
#---------------------------------------------

.equ		AIC_PRIOR,									0x07			/* Priority */

.equ		AIC_SRCTYPE,								0x60			/* Source Type Definition */
.equ		AIC_SRCTYPE_INT_LEVEL_SENSITIVE,			0x00			/* Level Sensitive */
.equ		AIC_SRCTYPE_INT_EDGE_TRIGGERED,				0x20			/* Edge Triggered */
.equ		AIC_SRCTYPE_EXT_LOW_LEVEL,					0x00			/* Low Level */
.equ		AIC_SRCTYPE_EXT_NEGATIVE_EDGE,				0x20			/* Negative Edge */
.equ		AIC_SRCTYPE_EXT_HIGH_LEVEL,					0x40			/* High Level */
.equ		AIC_SRCTYPE_EXT_POSITIVE_EDGE,				0x60			/* Positive Edge */

#--------------------------------------
#-  AIC_ISR: Interrupt Status Register
#--------------------------------------

.equ		AIC_IRQID,			0x1F									/* Current source interrupt */

#-------------------------------------------
#- AIC_CISR: Interrupt Core Status Register
#-------------------------------------------

.equ		AIC_NFIQ,			0x01									/* Core FIQ Status */
.equ		AIC_NIRQ,			0x02									/* Core IRQ Status */

#--------------------------------------------
#- Advanced Interrupt COntroller BAse Address
#--------------------------------------------

.equ		AIC_BASE,			0xFFFFF000

#	END