wd.inc

ATMEL公司的arm7处理器AT91R4008的库函数,我之前做的一个项目里面使用到的,在此网站上发现没有类似的资料,贡献给大家,能用到的最好.

#------------------------------------------------------------------------------
#-         ATMEL Microcontroller Software Support  -  ROUSSET  -
#------------------------------------------------------------------------------
# The software is delivered "AS IS" without warranty or condition of any
# kind, either express, implied or statutory. This includes without
# limitation any warranty or condition with respect to merchantability or
# fitness for any particular purpose, or against the infringements of
# intellectual property rights of others.
#------------------------------------------------------------------------------
#- File Name            : wd.inc
#- Object               : Assembler Watch Dog Definition File.
#-
#- 1.0 01/04/00 JCZ     : Creation
#------------------------------------------------------------------------------

#-----------------------------------------------
# Watch Dog User Interface Structure Definition
#-----------------------------------------------
.equ	WD_OMR,       0x00           /* Overflow Mode Register */
.equ	WD_CMR,       0x04           /* Counter Mode Register */
.equ	WD_CR,        0x08           /* Control Register */
.equ	WD_SR,        0x0C           /* Status Register */
#;                    0x10           /* Reserved */
.equ	WD_TLR,       0x14           /* Test Load Register : test purpose only */

#-----------------------------------------------------------
#- WD_OMR: Watch Dog Overflow Mode Register Bits Definition
#-----------------------------------------------------------

.equ	WD_WDEN,      0x01        	/* Watch Dog Enable */
.equ	WD_RSTEN,     0x02        	/* Internal Reset Enable */
.equ	WD_IRQEN,     0x04        	/* Interrupt Enable */
.equ	WD_EXTEN,     0x08        	/* External Signal Enable */
.equ	WD_OKEY,      0x2340      	/* Overflow Mode Register Access Key */

#---------------------------------------------------
#- WD_CMR: Watch Dog Clock Register Bits Definition
#---------------------------------------------------

.equ	WD_WDCLKS,                0x03        /* Clock Selection */
.equ	WD_WDCLKS_MCK8,           0x0
.equ	WD_WDCLKS_MCK32,          0x1
.equ	WD_WDCLKS_MCK128,         0x2
.equ	WD_WDCLKS_MCK1024,        0x3

.equ	WD_HPCV,                  (0x0F<<2)    /* High Preload Counter Value */

.equ	WD_CKEY,                  (0x06E<<7)   /* Clock Register Access Key */

#----------------------------------------------------
#- WD_CR: Watch Dog Control Register Bits Definition
#----------------------------------------------------

.equ	WD_RSTKEY,           0xC071      /* Watch Dog Restart Key */

#---------------------------------------------------
#- WD_SR: Watch Dog Status Register Bits Definition
#---------------------------------------------------

.equ	WD_WDOVF,            0x1         /* WatchDog Overflow Status */


#----------------------------------------------------
#-  WD_TLR: Test Load Register for test purpose only
#----------------------------------------------------

.equ	WD_TMRKEY,           0xD64A0000  /* Access Key */
.equ	WD_TESTEN,           0x2         /* Test Mode Enable */

#                END