apmc55800.inc

ATMEL公司的arm7处理器AT91R4008的库函数,我之前做的一个项目里面使用到的,在此网站上发现没有类似的资料,贡献给大家,能用到的最好.

#------------------------------------------------------------------------------
#-         ATMEL Microcontroller Software Support  -  ROUSSET  -
#------------------------------------------------------------------------------
# The software is delivered "AS IS" without warranty or condition of any
# kind, either express, implied or statutory. This includes without
# limitation any warranty or condition with respect to merchantability or
# fitness for any particular purpose, or against the infringements of
# intellectual property rights of others.
#------------------------------------------------------------------------------
#- File Name            : apmc55800.inc
#- Object               : Assembler Power Management Controller Definition File.
#-
#- 1.0 04/07/00  PF     : Creation
#------------------------------------------------------------------------------

#--------------------------------------------------------------------------
#- Advanced Power Management Controller User Interface Structure Definition
#--------------------------------------------------------------------------
#               ^       0
.EQU	C_SCER,      0x00       /* Source Clock Enable Register */
.EQU	APMC_SCDR,   0x04       /* Source Clock Disable Register */
.EQU	APMC_SCSR,   0x08       /* Source Clock Mask Register */
                #    0x0C       /* Reserved */
.EQU	APMC_PCER,   0x10       /* Peripheral Clock Enable Register */
.EQU	APMC_PCDR,   0x14       /* Peripheral Clock Disable Register */
.EQU	APMC_PCSR,   0x18       /* Peripheral Clock Status Register */
                #    0x1C       /* Reserved */
.EQU	APMC_CGMR,   0x20       /* Clock Generator Mode Register */
                #    0x24       /* Reserved */
.EQU	APMC_PCR,    0x28       /* Power Control Register */
.EQU	APMC_PMR,    0x2C       /* Power Mode Register */
.EQU	APMC_SR,     0x30       /* Status Register   */
.EQU	APMC_IER,    0x34       /* Interrupt Enable Register   */
.EQU	APMC_IDR,    0x38       /* Interrupt Disable Register   */
.EQU	APMC_IMR,    0x40       /* Interrupt Mask Register   */

#------------------------
#- System Clock Registers
#------------------------

.EQU	ARM7DIS,   		0x1

#------------------------------------------------------------
#- Advanced Power Managment Control Register Bits Definition 
#------------------------------------------------------------
.EQU	APMC_ARM7DIS,	0x1

#-------------------------------------------------------------------------
#- Advanced Power Managment Clock Generator Mode Register Bits Definition 
#-------------------------------------------------------------------------
.EQU	APMC_MOSC_BYP,	0x1     /* Main Oscillator Bypass */
.EQU	MOSCS_MASK,   	0x1
.EQU	PLL_LOCK_MASK,  0x2

.EQU	APMC_MOSC_EN,   0x2     /* Main Oscillator Enable  */
.EQU	APMC_MCKO_DIS,  0x4     /* Disable Master clock output (tri-state)  */

.EQU	APMC_PRES_NONE, 0x0     /* No prescaler  */
.EQU	APMC_PRES_DIV2, 0x10    /* Selected Clock Divided by 2  */
.EQU	APMC_PRES_DIV4, 0x20    /* Selected Clock Divided by 4  */
.EQU	APMC_PRES_DIV8, 0x30    /* Selected Clock Divided by 8  */
.EQU	APMC_PRES_DIV16,	0x40    /* Selected Clock Divided by 16  */
.EQU	APMC_PRES_DIV32,	0x50    /* Selected Clock Divided by 32  */
.EQU	APMC_PRES_DIV64,	0x60    /* Selected Clock Divided by 64  */

.EQU	APMC_CSS_LF,    0x0     /* Low-Frequency Clock provided by RTC  */
.EQU	APMC_CSS_MOSC,  0x4000  /* Main Oscillator Output or External clock  */
.EQU	APMC_CSS_PLL,   0x8000  /* Phase Lock Loop Output  */

.EQU	B_MUL,          8
.EQU	B_OSCOUNT,      16
.EQU	B_PLLCOUNT,     24

#-------------------------------------------------
#- APM Power Controller Register Bits Definition  
#-------------------------------------------------
.EQU	APMC_SHDALC,    0x1     /* Shut-down or alarm Command */ 
.EQU	APMC_WKACKC,    0x2     /* Wake-up or Alarm Acknowledge Command      */

#------------------------------------------------
#- APM Power Mode Register Bits Definition       
#------------------------------------------------
.EQU	APMC_SHDALS_OUT_TRIS,        0x0     /* SHDALS pin is Tri-State  */
.EQU	APMC_SHDALS_OUT_LEVEL_0,     0x1     /* SHDALS pin is LEVEL 0  */
.EQU	APMC_SHDALS_OUT_LEVEL_1,     0x2     /* SHDALS pin LEVEL 1  */

.EQU	APMC_WKACKS_OUT_TRIS,        0x0     /* WKACKS pin is Tri-State  */
.EQU	APMC_WKACKS_OUT_LEVEL_0,     0x4     /* WKACKS pin  is LEVEL 0  */
.EQU	APMC_WKACKS_OUT_LEVEL_1,     0x8     /* WKACKS pin  is LEVEL 1  */

.EQU	APMC_WKEN,                   0x10    /* Alarm Wake-up Enable  */
.EQU	APMC_ALSHEN,                 0x20    /* Alarm Shut-Down Enable  */

.EQU	APMC_WKEDG_NONE,             0x00    /* None. No edge is detected on Wake-up  */
.EQU	APMC_WKEDG_POS_EDG,          0x40    /* Positive edge detection  */
.EQU	APMC_WKEDG_NEG_EDG,          0x80    /* Negative edge detection  */

#-------------------------------------------------------
#- APM SR, IER, IDR and IMR Registers Bits Definition   
#-------------------------------------------------------
.EQU	APMC_MOSCS,                  0x1     /* Main Osillator Status  */
.EQU	APMC_PLL_LOCK,               0x2     /* PLL Lock Status  */


#-----------------------------------------
# Power Management Controller Base Address
#-----------------------------------------

.EQU	APMC_BASE,                   0xFFFF4000

#           END