pmc42800.inc

ATMEL公司的arm7处理器AT91R4008的库函数,我之前做的一个项目里面使用到的,在此网站上发现没有类似的资料,贡献给大家,能用到的最好.

#;------------------------------------------------------------------------------
#;-         ATMEL Microcontroller Software Support  -  ROUSSET  -
#;------------------------------------------------------------------------------
#; The software is delivered "AS IS" without warranty or condition of any
#; kind, either express, implied or statutory. This includes without
#; limitation any warranty or condition with respect to merchantability or
#; fitness for any particular purpose, or against the infringements of
#; intellectual property rights of others.
#;------------------------------------------------------------------------------
#;- File Name            : pmc42800.inc
#;- Object               : Assembler Power Management Controller Definition File.
#;-
#;- 1.0 04/07/00  PF     : Creation
#;------------------------------------------------------------------------------

#;------------------------------------------------------------------
#;- Power Management Controller User Interface Structure Definition
#;------------------------------------------------------------------
#                ^       0
.EQU	PMC_SCER,        0x00              /* Source Clock Enable Register */
.EQU	PMC_SCDR,        0x04              /* Source Clock Disable Register */
.EQU	PMC_SCSR,        0x08              /* Source Clock Mask Register */
@                        0x0C	           /* Reserved */
.EQU	PMC_PCER,        0x10              /* Peripheral Clock Enable Register */
.EQU	PMC_PCDR,        0x14              /* Peripheral Clock Disable Register */
.EQU	PMC_PCSR,        0x18              /* Peripheral Clock Status Register */
#						 			       /* Reserved */
.EQU	PMC_CGMR, 		 0x1C       		/* Clock Generator Mode Register */
@						 0x20				/* Reserved */
@						 0x24				/* Reserved */
@						 0x28				/* Reserved */
.EQU	PMC_SR,			 0x2C	    	    /* Status Register   */
.EQU	PMC_IER,		 0x30				/* Interrupt Enable Register   */
.EQU	PMC_IDR, 		 0x34				/* Interrupt Disable Register   */
.EQU	PMC_IMR, 		 0x38				/* Interrupt Mask Register   */

#;------------------------
#;- System Clock Registers
#;------------------------

.EQU	ARM7DIS,              0x1

#;-------------------------------------------------------
#;- PM SR, IER, IDR and IMR Registers Bits Definition   
#;-------------------------------------------------------
.EQU	PMC_PLL_LOCK,          0x1     		/* - PLL Lock Status */

#;-----------------------------------------
#; Power Management Controller Base Address
#;-----------------------------------------

.EQU	PMC_BASE,             0xFFFF4000

#            END