st.inc

ATMEL公司的arm7处理器AT91R4008的库函数,我之前做的一个项目里面使用到的,在此网站上发现没有类似的资料,贡献给大家,能用到的最好.

#----------------------------------------------------------------------------
#         ATMEL Microcontroller Software Support  -  ROUSSET  -
#----------------------------------------------------------------------------
# The software is delivered "AS IS" without warranty or condition of any
# kind, either express, implied or statutory. This includes without
# limitation any warranty or condition with respect to merchantability or
# fitness for any particular purpose, or against the infringements of
# intellectual property rights of others.
#----------------------------------------------------------------------------
# File Name           : st.inc
# Object              : System Timer Assembly File.
#
# 1.0 10/06/01  PF    : Creation
#----------------------------------------------------------------------------

#---------------------------------------------------
#  System Timer User Interface Structure Definition 
#---------------------------------------------------
.EQU	ST_CR, 		0x0 		@ Control Register
.EQU	ST_PIMR,	0x4 		@ Period Interval Mode Register
.EQU	ST_WDMR,	0x8 		@ Watchdog Mode Register
.EQU	ST_RTMR,	0xc 		@ Real Time Mode Register
.EQU	ST_SR, 		0x10		@ Status Register
.EQU	ST_IER,		0x14		@ Interrupt Enable Register
.EQU	ST_IDR,		0x18		@ Interrupt Disable Register
.EQU	ST_IMR,		0x1c		@ Interrupt Mask Register
.EQU	ST_RTAR,	0x20		@ Real Time Alarm Register
.EQU	ST_CRTR,	0x24		@ Current Real Time Register


#----------------------------------------------------------
# ST_CR: System Timer Control Register Bits Definition 
#---------------------------------------------------------
.EQU	ST_WDRST,	0x1 		@ Watchdog Timer Restart

#---------------------------------------------------------------
# ST_WDMR: System Timer Watchdog Mode Register Bits Definition
#---------------------------------------------------------------
.EQU	ST_RSTEN,   0x10000     @ WatchDog Overflow Reset Enable
.EQU	ST_EXTEN,   0x20000     @ External Signal Assertion Enable


#--------------------------------------------------------------------------------------------
# ST_SR, ST_IER, ST_IDR, ST_IMR : System Timer Status and Interrupts Register Bits Definition
#--------------------------------------------------------------------------------------------
.EQU	ST_PITS,    0x1     	@ Period Interval Timer Status
.EQU	ST_WDOVF,   0x2     	@ WatchDog Overflow Status
.EQU	ST_RTTINC,  0x4     	@ Real Time Timer Increment
.EQU	ST_ALMS,    0x8     	@ Alarm Status

#    .END