init.s

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    mov r1,#256
0   subs r1,r1,#1                   ; 1) wait until the SelfRefresh is released.
    bne %B0        
    
    ldr r1,=GSTATUS3                ; GSTATUS3 has the start address just after POWER_OFF wake-up
    ldr r0,[r1]
    mov pc,r0

    LTORG   
HandlerFIQ     HANDLER HandleFIQ
HandlerIRQ     HANDLER HandleIRQ
HandlerUndef   HANDLER HandleUndef
HandlerSWI     HANDLER HandleSWI
HandlerDabort  HANDLER HandleDabort
HandlerPabort  HANDLER HandlePabort


;*****************************************************************************
;
; ResetHandler is the startup code to be used
;
;*****************************************************************************
ResetHandler
        ldr    r0,=WTCON            ; watch dog disable 
        ldr    r1,=0x0         
        str    r1,[r0]

        ldr    r0,=INTMSK
        ldr    r1,=0xffffffff       ; all interrupt disable
        str    r1,[r0]

        ldr    r0,=INTSUBMSK
        ldr    r1,=0x7ff            ; all sub interrupt disable
        str    r1,[r0]

        ; To reduce PLL lock time, adjust the LOCKTIME register. 
        ldr    r0,=LOCKTIME
        ldr    r1,=0xffffff
        str    r1,[r0]
        
        ;
        ;by pht.
        ;
        ldr	r0, =CLKDIVN
        ldr	r1, =0x03
        str	r1,[r0]
        
        ldr	r0, =UPLLCON
        ldr	r1, =0x00048032
        str	r1,[r0]
        
        [ PLL_ON_START
            ; Configure MPLL
            ldr    r0,=MPLLCON          
            ldr    r1,=((M_MDIV<<12)+(M_PDIV<<4)+M_SDIV)  ; Fin=12MHz,Fout=50MHz
            str    r1,[r0]
        ]
        
        


        ; Check if the boot is caused by the wake-up from POWER_OFF mode.
        ldr    r1,=GSTATUS2
        ldr    r0,[r1]
        tst    r0,#0x2
        ; In case of the wake-up from POWER_OFF mode, go to POWER_OFF_WAKEUP handler. 
        bne    WAKEUP_POWER_OFF

        EXPORT StartPointAfterPowerOffWakeUp
StartPointAfterPowerOffWakeUp

	    mrc	p15, 0, r1, c1, c0, 0		; read ctrl register 
		orr	r1, r1, #0xc0000000			; Asynchronous  
		mcr	p15, 0, r1, c1, c0, 0		; write ctrl register

        ; Set memory control registers
        ldr    r0,=SMRDATA
        ldr    r1,=BWSCON           ; BWSCON Address
        add    r2, r0, #52          ; End address of SMRDATA
0       
        ldr    r3, [r0], #4    
        str    r3, [r1], #4    
        cmp    r2, r0        
        bne    %B0

        ; Initialize stacks
        bl InitStacks
    
;********************************************************************
; End of Stack Setup
;********************************************************************
	
;********************************************************************
;初始化内存
		bl memsetup
;初始化串口
		bl InitUART
;********************************************************************

program
        ;
        ; Call the actual C program.
        ; Should never return.
        ;
        IMPORT C_vMain
        b C_vMain                   ; C Entry
        
;********************************************************************
;初始化串口
;********************************************************************
InitUART
	
		ldr r1, =GPHCON
		ldr	r2, =vGPHCON	
		str	r2, [r1]
		
		ldr r1, =GPHUP
		ldr	r2, =vGPHUP
		str	r2, [r1]

		ldr	r1, =SerBase
		mov	r2, #0x0
		str	r2, [r1, #oUMCON0]
		mov r2, #0xf7
		str	r2, [r1, #oUFCON0]
		mov	r2, #0x3
		str	r2, [r1, #oULCON0]
		ldr	r2, =0x245
		str	r2, [r1, #oUCON0]
	
		ldr	r2, =UART_BRD
		str	r2, [r1, #oUBRDIV0]

		mov	r3, #100
		mov	r2, #0x0
0	
		sub	r3, r3, #0x1
		cmp	r2, r3
		bne	%B0
		
		mov pc, lr
;********************************************************************
;Memsetup函数的实现：by pht
;********************************************************************

memsetup

		mov	r1, #MEM_CTL_BASE
		ldr r0,=vBWSCON
		str r0,[r1],#4
		
		ldr r0,=vBANKCON0
		str r0,[r1],#4		
		
		ldr r0,=vBANKCON1
		str r0,[r1],#4
		
		ldr r0,=vBANKCON2
		str r0,[r1],#4
		
		ldr r0,=vBANKCON3
		str r0,[r1],#4
		
		ldr r0,=vBANKCON4
		str r0,[r1],#4
		
		ldr r0,=vBANKCON5
		str r0,[r1],#4
		
		ldr r0,=vBANKCON6
		str r0,[r1],#4
		
		ldr r0,=vBANKCON7
		str r0,[r1],#4
		
		ldr r0,=vREFRESH
		str r0,[r1],#4
		
		ldr r0,=vBANKSIZE
		str r0,[r1],#4
		
		ldr r0,=vMRSRB6
		str r0,[r1],#4
		
		ldr r0,=vMRSRB7
		str r0,[r1],#4

		mov	pc, lr
		
;********************************************************************
InitStacks
        ; Dont use DRAM,such as stmfd,ldmfd......
        ; SVCstack is initialized before
        ; Under toolkit ver 2.50, 'msr cpsr,r1' can be used instead of 'msr cpsr_cxsf,r1'
        
        mrs r0,cpsr
        bic r0,r0,#MODEMASK
        orr r1,r0,#UNDEFMODE|NOINT
        msr cpsr_cxsf,r1            ; UndefMode
        ldr sp,=UndefStack
        
        orr r1,r0,#ABORTMODE|NOINT
        msr cpsr_cxsf,r1            ; AbortMode
        ldr sp,=AbortStack

        orr r1,r0,#IRQMODE|NOINT
        msr cpsr_cxsf,r1            ; IRQMode
        ldr sp,=IRQStack
        
        orr r1,r0,#FIQMODE|NOINT
        msr cpsr_cxsf,r1            ; FIQMode
        ldr sp,=FIQStack

        bic r0,r0,#MODEMASK|NOINT
        orr r1,r0,#SVCMODE
        msr cpsr_cxsf,r1            ; SVCMode
        ldr sp,=SVCStack

        ; USER mode is not initialized.

        mov pc,lr                   ; The LR register may be not valid for the mode changes.

    LTORG

SMRDATA DATA
; Memory configuration should be optimized for best performance 
; The following parameter is not optimized.                     
; Memory access cycle parameter strategy
; 1) The memory settings is  safe parameters even at HCLK=75Mhz.
; 2) SDRAM refresh period is for HCLK=75Mhz. 

        DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
        DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ;GCS0
        DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ;GCS1 
        DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ;GCS2
        DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ;GCS3
        DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ;GCS4
        DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ;GCS5
        DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))    ;GCS6
        DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))    ;GCS7
        DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)    



        DCD 0x32                    ; SCLK power saving mode, BANKSIZE 128M/128M

        DCD 0x30                    ; MRSR6 CL=3clk
        DCD 0x30                    ; MRSR7
;        DCD 0x20                    ; MRSR6 CL=2clk
;        DCD 0x20                    ; MRSR7

;
;*****************************************************************************
;
; Zero-initialized read/write data area for stacks.
; This area is determined by the RW value in the Linker under "entry and base".  
;*****************************************************************************
        AREA  SYS_STK, DATA, READWRITE, NOINIT

;*****************************************************************************
;
; Memory buffers to contain the stacks for the various processor modes which
; we will be using.
;
;*****************************************************************************

        ^       STK_SADDR

UserStack       #       _SVC_STKSIZE
SVCStack        #       _UND_STKSIZE
UndefStack      #       _ABT_STKSIZE
AbortStack      #       _IRQ_STKSIZE
IRQStack        #       _FIQ_STKSIZE
FIQStack        #       0 


        AREA  ISR_HOOK, DATA, READWRITE, NOINIT

        ^  ISR_BADDR
HandleReset     # 4
HandleUndef     # 4
HandleSWI       # 4
HandlePabort    # 4
HandleDabort    # 4
HandleReserved  # 4
HandleIRQ       # 4
HandleFIQ       # 4

;
;*****************************************************************************
;
        END