ad.vhd

ａｄ采样ＶＨＤＬ程序

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:04:36 11/11/2007 
-- Design Name: 
-- Module Name:    ad - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
entity ad is 
port(d:in std_logic_vector(7 downto 0); 
     rst,clk,eoc:in std_logic; 
     ale,start,oe,adda:out std_logic; 
     dout:out std_logic_vector(11 downto 0)); 
end; 
architecture one of ad is 
type state is(t0,t1,t2,t3,t4,t5,t6); 
signal current_state,next_state:state; 
signal regl:std_logic_vector(7 downto 0); 
signal lock0,lock1:std_logic; 
signal value:std_logic_vector(11 downto 0); 
signal cen:std_logic; 
signal ale0:std_logic; 
signal start0:std_logic; 
signal oe0:std_logic; 
begin 
system:block is 
begin 
adda<='1'; 
process(current_state,eoc) 
begin 
case current_state is 
    when t0=>ale0<='0';start0<='0';oe0<='0'; 
         lock0<='0';next_state<=t1;cen<='0'; 
    when t1=>ale0<='1';start0<='0';oe0<='0'; 
         lock0<='0';next_state<=t2;cen<='0'; 
    when t2=>ale0<='0';start0<='1';oe0<='0'; 
         lock0<='0';next_state<=t3;cen<='0'; 
    when t3=>ale0<='0';start0<='0';oe0<='0'; 
         lock0<='0'; 
         if eoc='1' then 
           next_state<=t3; 
         else 
           next_state<=t4; 
         end if; 
    when t4=>ale0<='0';start0<='0';oe0<='0'; 
         lock0<='0';cen<='0'; 
         if eoc='1' then 
           next_state<=t4; 
         else 
           next_state<=t5; 
         end if;             
    when t5=>ale0<='0';start0<='0';oe0<='1'; 
         lock0<='0';next_state<=t6;cen<='1'; 
    when t6=>ale0<='0';start0<='0';oe0<='0'; 
         lock0<='1';next_state<=t0;cen<='0'; 
end case; 
end process;  
process(rst,clk) 
begin 
if rst='1' then 
   current_state<=t0; 
elsif rising_edge(clk) then 
     current_state<=next_state; 
end if; 
end process; 
process(clk) 
begin 
if rising_edge(clk) then 
  ale<=ale0;start<=start0;oe<=oe0;lock1<=lock0; 
end if; 
end process; 
process(lock1) 
begin 
if rising_edge(lock1) then 
  regl<=d; 
end if; 
end process; 
end block system; 
convention:block is 
signal v:std_logic_vector(7 downto 0); 
signal hb,lb:std_logic_vector(11 downto 0); 
signal c30,c74,c118:std_logic; 
signal tempa,tempb,tempc:std_logic_vector(3 downto 0); 
begin 
process(regl) 
begin 
v<=regl; 
case v(7 downto 4) is 
    when"1111"=>hb<="010010000000"; 
    when"1110"=>hb<="010001001000"; 
    when"1101"=>hb<="010000010110"; 
    when"1100"=>hb<="001110000100"; 
    when"1011"=>hb<="010010000000"; 
    when"1010"=>hb<="001101010010"; 
    when"1001"=>hb<="001010001000"; 
    when"1000"=>hb<="001001010110"; 
    when"0111"=>hb<="001000100100"; 
    when"0110"=>hb<="000110010010"; 
    when"0101"=>hb<="000101100000"; 
    when"0100"=>hb<="000100101000"; 
    when"0011"=>hb<="000010010110"; 
    when"0010"=>hb<="000001100100"; 
    when"0001"=>hb<="000001100010"; 
    when others=>hb<="000000000000"; 
end case; 
case v(3 downto 0) is 
    when"1111"=>lb<="000000110000"; 
    when"1110"=>lb<="000000101000"; 
    when"1101"=>lb<="000000100110"; 
    when"1100"=>lb<="000000100100"; 
    when"1011"=>lb<="000000100010"; 
    when"1010"=>lb<="000000100000"; 
    when"1001"=>lb<="000000011000"; 
    when"1000"=>lb<="000000010110"; 
    when"0111"=>lb<="000000010100"; 
    when"0110"=>lb<="000000010010"; 
    when"0101"=>lb<="000000010000"; 
    when"0100"=>lb<="000000001000"; 
    when"0011"=>lb<="000000000110"; 
    when"0010"=>lb<="000000000100"; 
    when"0001"=>lb<="000000000010"; 
    when others=>lb<="000000000000"; 
end case; 
end process; 
process(hb,lb,cen) 
variable temp1,temp2,temp3:std_logic_vector(3 downto 0); 
begin 
if rising_edge(cen) then 
   temp1:=hb(3 downto 0)+lb(3 downto 0); 
if temp1>"1001" then 
    temp1:=temp1+"0110"; 
   temp2:=hb(7 downto 4)+lb(7 downto 4); 
if temp2>"1001" then 
    temp2:=temp2+"0110"; 
   temp3:=hb(11 downto 8)+lb(11 downto 0); 
if temp3>"1001" then 
    temp3:=temp3+"0110"; 
end if; 
    else 
    temp3:=hb(11 downto 8)+lb(11 downto 0); 
     if temp3>"1001" then 
    temp3:=temp3+"0110";     
end if; 
end if; 
else 
  temp2:=hb(7 downto 4)+lb(7 downto 4); 
if temp2>"1001" then 
    temp2:=temp2+"0110"; 
    temp3:=hb(11 downto 8)+lb(11 downto 0); 
     if temp3>"1001" then 
    temp3:=temp3+"0110";     
end if; 
else 
  temp3:=hb(11 downto 8)+lb(11 downto 0); 
     if temp3>"1001" then 
    temp3:=temp3 +"0110";     
end if; 
end if; 
end if; 
end if; 
value<=temp3&temp2&temp1; 
end process; 
dout<=value; 
end block convention; 
end one;