📄 at91sam7s64.inc
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US_IMR # 4 ;- Interrupt Mask Register
US_CSR # 4 ;- Channel Status Register
US_RHR # 4 ;- Receiver Holding Register
US_THR # 4 ;- Transmitter Holding Register
US_BRGR # 4 ;- Baud Rate Generator Register
US_RTOR # 4 ;- Receiver Time-out Register
US_TTGR # 4 ;- Transmitter Time-guard Register
# 20 ;- Reserved
US_FIDI # 4 ;- FI_DI_Ratio Register
US_NER # 4 ;- Nb Errors Register
# 4 ;- Reserved
US_IF # 4 ;- IRDA_FILTER Register
# 176 ;- Reserved
US_RPR # 4 ;- Receive Pointer Register
US_RCR # 4 ;- Receive Counter Register
US_TPR # 4 ;- Transmit Pointer Register
US_TCR # 4 ;- Transmit Counter Register
US_RNPR # 4 ;- Receive Next Pointer Register
US_RNCR # 4 ;- Receive Next Counter Register
US_TNPR # 4 ;- Transmit Next Pointer Register
US_TNCR # 4 ;- Transmit Next Counter Register
US_PTCR # 4 ;- PDC Transfer Control Register
US_PTSR # 4 ;- PDC Transfer Status Register
;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break
AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break
AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out
AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address
AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations
AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge
AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out
AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable
AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable
AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable
AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable
;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode
AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock
AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1
AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK)
AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit
AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits
AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order
AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select
AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode
AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge
AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK
AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions
AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter
;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached
AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge
AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag
AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag
AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag
AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag
;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input
AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input
AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input
AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Two-wire Interface
;- *****************************************************************************
^ 0 ;- AT91S_TWI
TWI_CR # 4 ;- Control Register
TWI_MMR # 4 ;- Master Mode Register
# 4 ;- Reserved
TWI_IADR # 4 ;- Internal Address Register
TWI_CWGR # 4 ;- Clock Waveform Generator Register
# 12 ;- Reserved
TWI_SR # 4 ;- Status Register
TWI_IER # 4 ;- Interrupt Enable Register
TWI_IDR # 4 ;- Interrupt Disable Register
TWI_IMR # 4 ;- Interrupt Mask Register
TWI_RHR # 4 ;- Receive Holding Register
TWI_THR # 4 ;- Transmit Holding Register
;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition
AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition
AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled
AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled
AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset
;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size
AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address
AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address
AT91C_TWI_IADRSZ_2_BYTE EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address
AT91C_TWI_IADRSZ_3_BYTE EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address
AT91C_TWI_MREAD EQU (0x1:SHL:12) ;- (TWI) Master Read Direction
AT91C_TWI_DADR EQU (0x7F:SHL:16) ;- (TWI) Device Address
;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
AT91C_TWI_CLDIV EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider
AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider
AT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider
;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission Completed
AT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY
AT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY
AT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun Error
AT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun Error
AT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged
;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
;- *****************************************************************************
^ 0 ;- AT91S_TC
TC_CCR # 4 ;- Channel Control Register
TC_CMR # 4 ;- Channel Mode Register (Capture Mode / Waveform Mode)
# 8 ;- Reserved
TC_CV # 4 ;- Counter Value
TC_RA # 4 ;- Register A
TC_RB # 4 ;- Register B
TC_RC # 4 ;- Register C
TC_SR # 4 ;- Status Register
TC_IER # 4 ;- Interrupt Enable Register
TC_IDR # 4 ;- Interrupt Disable Register
TC_IMR # 4 ;- Interrupt Mask Register
;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command
AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command
AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command
;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
AT91C_TC_CLKS EQU (0x7:SHL:0) ;- (TC) Clock Selection
AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
AT91C_TC_CLKI EQU (0x1:SHL:3) ;- (TC) Clock Invert
AT91C_TC_BURST EQU (0x3:SHL:4) ;- (TC) Burst Signal Selection
AT91C_TC_BURST_NONE EQU (0x0:SHL:4) ;- (TC) The clock is not gated by an external signal
AT91C_TC_BURST_XC0 EQU (0x1:SHL:4) ;- (TC) XC0 is ANDed with the selected clock
AT91C_TC_BURST_XC1 EQU (0x2:SHL:4) ;- (TC) XC1 is ANDed with the selected clock
AT91C_TC_BURST_XC2 EQU (0x3:SHL:4) ;- (TC) XC2 is ANDed with the selected clock
AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare
AT91C_TC_LDBSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RB Loading
AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare
AT91C_TC_LDBDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disabled with RB Loading
AT91C_TC_ETRGEDG EQU (0x3:SHL:8) ;- (TC) External Trigger Edge Selection
AT91C_TC_ETRGEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
AT91C_TC_ETRGEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
AT91C_TC_ETRGEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
AT91C_TC_ETRGEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection
AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection
AT91C_TC_EEVT_TIOB EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
AT91C_TC_EEVT_XC0 EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
AT91C_TC_EEVT_XC1 EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
AT91C_TC_EEVT_XC2 EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
AT91C_TC_ABETRG EQU (0x1:SHL:10) ;- (TC) TIOA or TIOB External Trigger Selection
AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable
AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection
AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare
AT91C_TC_WAVESEL_UPDOWN EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
AT91C_TC_WAVESEL_UP_AUTO EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare
AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable
AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC)
AT91C_T⌨️ 快捷键说明
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