📄 delay.hier_info
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|delay
Din => Din~0.IN1
Dout <= d:my_d12.out
clk => clk~0.IN12
rst => rst~0.IN12
|delay|d:my_d1
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d2
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d3
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d4
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d5
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d6
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d7
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d8
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d9
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d10
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d11
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
|delay|d:my_d12
in => out~reg0.DATAIN
out <= out~reg0.DB_MAX_OUTPUT_PORT_TYPE
clr_n => out~reg0.ACLR
clk => out~reg0.CLK
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