delay.tan.qmsg

在Quartus下使用D触发器来加入延迟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register d:my_d6\|out d:my_d7\|out 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"d:my_d6\|out\" and destination register \"d:my_d7\|out\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.636 ns + Longest register register " "Info: + Longest register to register delay is 0.636 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d:my_d6\|out 1 REG LCFF_X1_Y1_N21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y1_N21; Fanout = 1; REG Node = 'd:my_d6\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { d:my_d6|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.307 ns) + CELL(0.245 ns) 0.552 ns d:my_d7\|out~feeder 2 COMB LCCOMB_X1_Y1_N26 1 " "Info: 2: + IC(0.307 ns) + CELL(0.245 ns) = 0.552 ns; Loc. = LCCOMB_X1_Y1_N26; Fanout = 1; COMB Node = 'd:my_d7\|out~feeder'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.552 ns" { d:my_d6|out d:my_d7|out~feeder } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.636 ns d:my_d7\|out 3 REG LCFF_X1_Y1_N27 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.636 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'd:my_d7\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { d:my_d7|out~feeder d:my_d7|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.329 ns ( 51.73 % ) " "Info: Total cell delay = 0.329 ns ( 51.73 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.307 ns ( 48.27 % ) " "Info: Total interconnect delay = 0.307 ns ( 48.27 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.636 ns" { d:my_d6|out d:my_d7|out~feeder d:my_d7|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "0.636 ns" { d:my_d6|out d:my_d7|out~feeder d:my_d7|out } { 0.000ns 0.307ns 0.000ns } { 0.000ns 0.245ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.357 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.537 ns) 2.357 ns d:my_d7\|out 3 REG LCFF_X1_Y1_N27 1 " "Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'd:my_d7\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.246 ns" { clk~clkctrl d:my_d7|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.74 % ) " "Info: Total cell delay = 1.526 ns ( 64.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.831 ns ( 35.26 % ) " "Info: Total interconnect delay = 0.831 ns ( 35.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d7|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d7|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.357 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.537 ns) 2.357 ns d:my_d6\|out 3 REG LCFF_X1_Y1_N21 1 " "Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N21; Fanout = 1; REG Node = 'd:my_d6\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.246 ns" { clk~clkctrl d:my_d6|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.74 % ) " "Info: Total cell delay = 1.526 ns ( 64.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.831 ns ( 35.26 % ) " "Info: Total interconnect delay = 0.831 ns ( 35.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d6|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d6|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d7|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d7|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d6|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d6|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.636 ns" { d:my_d6|out d:my_d7|out~feeder d:my_d7|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "0.636 ns" { d:my_d6|out d:my_d7|out~feeder d:my_d7|out } { 0.000ns 0.307ns 0.000ns } { 0.000ns 0.245ns 0.084ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d7|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d7|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d6|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d6|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { d:my_d7|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { d:my_d7|out } {  } {  } } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "d:my_d1\|out Din clk 3.630 ns register " "Info: tsu for register \"d:my_d1\|out\" (data pin = \"Din\", clock pin = \"clk\") is 3.630 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.023 ns + Longest pin register " "Info: + Longest pin to register delay is 6.023 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns Din 1 PIN PIN_42 1 " "Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'Din'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.797 ns) + CELL(0.366 ns) 6.023 ns d:my_d1\|out 2 REG LCFF_X1_Y1_N13 1 " "Info: 2: + IC(4.797 ns) + CELL(0.366 ns) = 6.023 ns; Loc. = LCFF_X1_Y1_N13; Fanout = 1; REG Node = 'd:my_d1\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.163 ns" { Din d:my_d1|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.226 ns ( 20.36 % ) " "Info: Total cell delay = 1.226 ns ( 20.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.797 ns ( 79.64 % ) " "Info: Total interconnect delay = 4.797 ns ( 79.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.023 ns" { Din d:my_d1|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.023 ns" { Din Din~combout d:my_d1|out } { 0.000ns 0.000ns 4.797ns } { 0.000ns 0.860ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.357 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.537 ns) 2.357 ns d:my_d1\|out 3 REG LCFF_X1_Y1_N13 1 " "Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N13; Fanout = 1; REG Node = 'd:my_d1\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.246 ns" { clk~clkctrl d:my_d1|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.74 % ) " "Info: Total cell delay = 1.526 ns ( 64.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.831 ns ( 35.26 % ) " "Info: Total interconnect delay = 0.831 ns ( 35.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d1|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d1|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.023 ns" { Din d:my_d1|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.023 ns" { Din Din~combout d:my_d1|out } { 0.000ns 0.000ns 4.797ns } { 0.000ns 0.860ns 0.366ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d1|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d1|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Dout d:my_d12\|out 6.205 ns register " "Info: tco from clock \"clk\" to destination pin \"Dout\" through register \"d:my_d12\|out\" is 6.205 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.357 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.537 ns) 2.357 ns d:my_d12\|out 3 REG LCFF_X1_Y1_N25 1 " "Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N25; Fanout = 1; REG Node = 'd:my_d12\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.246 ns" { clk~clkctrl d:my_d12|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.74 % ) " "Info: Total cell delay = 1.526 ns ( 64.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.831 ns ( 35.26 % ) " "Info: Total interconnect delay = 0.831 ns ( 35.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d12|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d12|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.598 ns + Longest register pin " "Info: + Longest register to pin delay is 3.598 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d:my_d12\|out 1 REG LCFF_X1_Y1_N25 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y1_N25; Fanout = 1; REG Node = 'd:my_d12\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { d:my_d12|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.799 ns) + CELL(2.799 ns) 3.598 ns Dout 2 PIN PIN_31 0 " "Info: 2: + IC(0.799 ns) + CELL(2.799 ns) = 3.598 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'Dout'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.598 ns" { d:my_d12|out Dout } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.799 ns ( 77.79 % ) " "Info: Total cell delay = 2.799 ns ( 77.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.799 ns ( 22.21 % ) " "Info: Total interconnect delay = 0.799 ns ( 22.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.598 ns" { d:my_d12|out Dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.598 ns" { d:my_d12|out Dout } { 0.000ns 0.799ns } { 0.000ns 2.799ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d12|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d12|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.598 ns" { d:my_d12|out Dout } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "3.598 ns" { d:my_d12|out Dout } { 0.000ns 0.799ns } { 0.000ns 2.799ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "d:my_d1\|out Din clk -3.400 ns register " "Info: th for register \"d:my_d1\|out\" (data pin = \"Din\", clock pin = \"clk\") is -3.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.357 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 12 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 49 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.537 ns) 2.357 ns d:my_d1\|out 3 REG LCFF_X1_Y1_N13 1 " "Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N13; Fanout = 1; REG Node = 'd:my_d1\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.246 ns" { clk~clkctrl d:my_d1|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.74 % ) " "Info: Total cell delay = 1.526 ns ( 64.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.831 ns ( 35.26 % ) " "Info: Total interconnect delay = 0.831 ns ( 35.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d1|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d1|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.023 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.023 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.860 ns) 0.860 ns Din 1 PIN PIN_42 1 " "Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'Din'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.797 ns) + CELL(0.366 ns) 6.023 ns d:my_d1\|out 2 REG LCFF_X1_Y1_N13 1 " "Info: 2: + IC(4.797 ns) + CELL(0.366 ns) = 6.023 ns; Loc. = LCFF_X1_Y1_N13; Fanout = 1; REG Node = 'd:my_d1\|out'" {  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.163 ns" { Din d:my_d1|out } "NODE_NAME" } } { "delay.v" "" { Text "E:/解码一/delay/delay.v" 82 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.226 ns ( 20.36 % ) " "Info: Total cell delay = 1.226 ns ( 20.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.797 ns ( 79.64 % ) " "Info: Total interconnect delay = 4.797 ns ( 79.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.023 ns" { Din d:my_d1|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.023 ns" { Din Din~combout d:my_d1|out } { 0.000ns 0.000ns 4.797ns } { 0.000ns 0.860ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl d:my_d1|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl d:my_d1|out } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.023 ns" { Din d:my_d1|out } "NODE_NAME" } } { "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/altera/quartus60/win/Technology_Viewer.qrui" "6.023 ns" { Din Din~combout d:my_d1|out } { 0.000ns 0.000ns 4.797ns } { 0.000ns 0.860ns 0.366ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}