delay.tan.rpt

在Quartus下使用D触发器来加入延迟

+-------------------------------------------------------------------+
; tsu                                                               ;
+-------+--------------+------------+------+-------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To          ; To Clock ;
+-------+--------------+------------+------+-------------+----------+
; N/A   ; None         ; 3.630 ns   ; Din  ; d:my_d1|out ; clk      ;
+-------+--------------+------------+------+-------------+----------+


+----------------------------------------------------------------------+
; tco                                                                  ;
+-------+--------------+------------+--------------+------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To   ; From Clock ;
+-------+--------------+------------+--------------+------+------------+
; N/A   ; None         ; 6.205 ns   ; d:my_d12|out ; Dout ; clk        ;
+-------+--------------+------------+--------------+------+------------+


+-------------------------------------------------------------------------+
; th                                                                      ;
+---------------+-------------+-----------+------+-------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To          ; To Clock ;
+---------------+-------------+-----------+------+-------------+----------+
; N/A           ; None        ; -3.400 ns ; Din  ; d:my_d1|out ; clk      ;
+---------------+-------------+-----------+------+-------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Nov 06 08:43:18 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off delay -c delay --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "d:my_d6|out" and destination register "d:my_d7|out"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.636 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y1_N21; Fanout = 1; REG Node = 'd:my_d6|out'
            Info: 2: + IC(0.307 ns) + CELL(0.245 ns) = 0.552 ns; Loc. = LCCOMB_X1_Y1_N26; Fanout = 1; COMB Node = 'd:my_d7|out~feeder'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.636 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'd:my_d7|out'
            Info: Total cell delay = 0.329 ns ( 51.73 % )
            Info: Total interconnect delay = 0.307 ns ( 48.27 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.357 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N27; Fanout = 1; REG Node = 'd:my_d7|out'
                Info: Total cell delay = 1.526 ns ( 64.74 % )
                Info: Total interconnect delay = 0.831 ns ( 35.26 % )
            Info: - Longest clock path from clock "clk" to source register is 2.357 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N21; Fanout = 1; REG Node = 'd:my_d6|out'
                Info: Total cell delay = 1.526 ns ( 64.74 % )
                Info: Total interconnect delay = 0.831 ns ( 35.26 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "d:my_d1|out" (data pin = "Din", clock pin = "clk") is 3.630 ns
    Info: + Longest pin to register delay is 6.023 ns
        Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'Din'
        Info: 2: + IC(4.797 ns) + CELL(0.366 ns) = 6.023 ns; Loc. = LCFF_X1_Y1_N13; Fanout = 1; REG Node = 'd:my_d1|out'
        Info: Total cell delay = 1.226 ns ( 20.36 % )
        Info: Total interconnect delay = 4.797 ns ( 79.64 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.357 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N13; Fanout = 1; REG Node = 'd:my_d1|out'
        Info: Total cell delay = 1.526 ns ( 64.74 % )
        Info: Total interconnect delay = 0.831 ns ( 35.26 % )
Info: tco from clock "clk" to destination pin "Dout" through register "d:my_d12|out" is 6.205 ns
    Info: + Longest clock path from clock "clk" to source register is 2.357 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N25; Fanout = 1; REG Node = 'd:my_d12|out'
        Info: Total cell delay = 1.526 ns ( 64.74 % )
        Info: Total interconnect delay = 0.831 ns ( 35.26 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.598 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y1_N25; Fanout = 1; REG Node = 'd:my_d12|out'
        Info: 2: + IC(0.799 ns) + CELL(2.799 ns) = 3.598 ns; Loc. = PIN_31; Fanout = 0; PIN Node = 'Dout'
        Info: Total cell delay = 2.799 ns ( 77.79 % )
        Info: Total interconnect delay = 0.799 ns ( 22.21 % )
Info: th for register "d:my_d1|out" (data pin = "Din", clock pin = "clk") is -3.400 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.357 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 12; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N13; Fanout = 1; REG Node = 'd:my_d1|out'
        Info: Total cell delay = 1.526 ns ( 64.74 % )
        Info: Total interconnect delay = 0.831 ns ( 35.26 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 6.023 ns
        Info: 1: + IC(0.000 ns) + CELL(0.860 ns) = 0.860 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'Din'
        Info: 2: + IC(4.797 ns) + CELL(0.366 ns) = 6.023 ns; Loc. = LCFF_X1_Y1_N13; Fanout = 1; REG Node = 'd:my_d1|out'
        Info: Total cell delay = 1.226 ns ( 20.36 % )
        Info: Total interconnect delay = 4.797 ns ( 79.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Nov 06 08:43:19 2007
    Info: Elapsed time: 00:00:01