delay.v

在Quartus下使用D触发器来加入延迟

/*module delay(Din,Dout,clk,rst);
input [7:0] Din;
input clk,rst;
output [7:0] Dout;

wire [7:0]out1;
d my_d1(.in(Din),.out(out1),.clr_n(rst),.clk(clk));
wire [7:0]out2;
d my_d2(.in(out1),.out(out2),.clr_n(rst),.clk(clk));
wire [7:0]out3;
d my_d3(.in(out2),.out(out3),.clr_n(rst),.clk(clk));
wire [7:0]out4;
d my_d4(.in(out3),.out(out4),.clr_n(rst),.clk(clk));
wire [7:0]out5;
d my_d5(.in(out4),.out(out5),.clr_n(rst),.clk(clk));
wire [7:0]out6;
d my_d6(.in(out5),.out(out6),.clr_n(rst),.clk(clk));
wire [7:0]out7;
d my_d7(.in(out6),.out(out7),.clr_n(rst),.clk(clk));
wire [7:0]out8;
d my_d8(.in(out7),.out(out8),.clr_n(rst),.clk(clk));
wire [7:0]out9;
d my_d9(.in(out8),.out(out9),.clr_n(rst),.clk(clk));
wire [7:0]out10;
d my_d10(.in(out9),.out(out10),.clr_n(rst),.clk(clk));
wire [7:0]out11;
d my_d11(.in(out10),.out(out11),.clr_n(rst),.clk(clk));
//wire [7:0]out12;
d my_d12(.in(out11),.out(Dout),.clr_n(rst),.clk(clk));
endmodule

module d (in,out,clr_n,clk);
input clk;
input clr_n;
input [7:0] in;
output[7:0] out;
reg [7:0] out;
always @(posedge clk or negedge clr_n)
begin
  if(clr_n==0)
    out<=0;
 else 
out<=in;
end
endmodule*/

module delay(Din,Dout,clk,rst);
input  Din;
input clk,rst;
output  Dout;

wire out1;
d my_d1(.in(Din),.out(out1),.clr_n(rst),.clk(clk));
wire out2;
d my_d2(.in(out1),.out(out2),.clr_n(rst),.clk(clk));
wire out3;
d my_d3(.in(out2),.out(out3),.clr_n(rst),.clk(clk));
wire out4;
d my_d4(.in(out3),.out(out4),.clr_n(rst),.clk(clk));
wire out5;
d my_d5(.in(out4),.out(out5),.clr_n(rst),.clk(clk));
wire out6;
d my_d6(.in(out5),.out(out6),.clr_n(rst),.clk(clk));
wire out7;
d my_d7(.in(out6),.out(out7),.clr_n(rst),.clk(clk));
wire out8;
d my_d8(.in(out7),.out(out8),.clr_n(rst),.clk(clk));
wire out9;
d my_d9(.in(out8),.out(out9),.clr_n(rst),.clk(clk));
wire out10;
d my_d10(.in(out9),.out(out10),.clr_n(rst),.clk(clk));
wire out11;
d my_d11(.in(out10),.out(out11),.clr_n(rst),.clk(clk));
//wire [7:0]out12;
d my_d12(.in(out11),.out(Dout),.clr_n(rst),.clk(clk));
endmodule

module d (in,out,clr_n,clk);
input clk;
input clr_n;
input  in;
output out;
reg  out;
always @(posedge clk or negedge clr_n)
begin
  if(clr_n==0)
    out<=0;
 else 
out<=in;
end
endmodule