delay.tan.qmsg

在Quartus下使用D触发器来加入延迟

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register de:comb_11\|out\[2\] de:comb_12\|out\[2\] 420.17 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 420.17 MHz between source register \"de:comb_11\|out\[2\]\" and destination register \"de:comb_12\|out\[2\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.38 ns " "Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.542 ns + Longest register register " "Info: + Longest register to register delay is 0.542 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns de:comb_11\|out\[2\] 1 REG LCFF_X1_Y1_N23 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y1_N23; Fanout = 1; REG Node = 'de:comb_11\|out\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { de:comb_11|out[2] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.309 ns) + CELL(0.149 ns) 0.458 ns de:comb_12\|out\[2\]~feeder 2 COMB LCCOMB_X1_Y1_N0 1 " "Info: 2: + IC(0.309 ns) + CELL(0.149 ns) = 0.458 ns; Loc. = LCCOMB_X1_Y1_N0; Fanout = 1; COMB Node = 'de:comb_12\|out\[2\]~feeder'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.458 ns" { de:comb_11|out[2] de:comb_12|out[2]~feeder } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 0.542 ns de:comb_12\|out\[2\] 3 REG LCFF_X1_Y1_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.542 ns; Loc. = LCFF_X1_Y1_N1; Fanout = 1; REG Node = 'de:comb_12\|out\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { de:comb_12|out[2]~feeder de:comb_12|out[2] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.233 ns ( 42.99 % ) " "Info: Total cell delay = 0.233 ns ( 42.99 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.309 ns ( 57.01 % ) " "Info: Total interconnect delay = 0.309 ns ( 57.01 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.542 ns" { de:comb_11|out[2] de:comb_12|out[2]~feeder de:comb_12|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.542 ns" { de:comb_11|out[2] de:comb_12|out[2]~feeder de:comb_12|out[2] } { 0.000ns 0.309ns 0.000ns } { 0.000ns 0.149ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.357 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 72 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.537 ns) 2.357 ns de:comb_12\|out\[2\] 3 REG LCFF_X1_Y1_N1 1 " "Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N1; Fanout = 1; REG Node = 'de:comb_12\|out\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.246 ns" { clk~clkctrl de:comb_12|out[2] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.74 % ) " "Info: Total cell delay = 1.526 ns ( 64.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.831 ns ( 35.26 % ) " "Info: Total interconnect delay = 0.831 ns ( 35.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl de:comb_12|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl de:comb_12|out[2] } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.357 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 72 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.709 ns) + CELL(0.537 ns) 2.357 ns de:comb_11\|out\[2\] 3 REG LCFF_X1_Y1_N23 1 " "Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N23; Fanout = 1; REG Node = 'de:comb_11\|out\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.246 ns" { clk~clkctrl de:comb_11|out[2] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.74 % ) " "Info: Total cell delay = 1.526 ns ( 64.74 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.831 ns ( 35.26 % ) " "Info: Total interconnect delay = 0.831 ns ( 35.26 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl de:comb_11|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl de:comb_11|out[2] } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl de:comb_12|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl de:comb_12|out[2] } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl de:comb_11|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl de:comb_11|out[2] } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.542 ns" { de:comb_11|out[2] de:comb_12|out[2]~feeder de:comb_12|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "0.542 ns" { de:comb_11|out[2] de:comb_12|out[2]~feeder de:comb_12|out[2] } { 0.000ns 0.309ns 0.000ns } { 0.000ns 0.149ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl de:comb_12|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl de:comb_12|out[2] } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.357 ns" { clk clk~clkctrl de:comb_11|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.357 ns" { clk clk~combout clk~clkctrl de:comb_11|out[2] } { 0.000ns 0.000ns 0.122ns 0.709ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { de:comb_12|out[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { de:comb_12|out[2] } {  } {  } } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "de:comb_4\|out\[3\] Din\[3\] clk 4.019 ns register " "Info: tsu for register \"de:comb_4\|out\[3\]\" (data pin = \"Din\[3\]\", clock pin = \"clk\") is 4.019 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.429 ns + Longest pin register " "Info: + Longest pin to register delay is 6.429 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns Din\[3\] 1 PIN PIN_103 1 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_103; Fanout = 1; PIN Node = 'Din\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[3] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.211 ns) + CELL(0.366 ns) 6.429 ns de:comb_4\|out\[3\] 2 REG LCFF_X19_Y13_N1 1 " "Info: 2: + IC(5.211 ns) + CELL(0.366 ns) = 6.429 ns; Loc. = LCFF_X19_Y13_N1; Fanout = 1; REG Node = 'de:comb_4\|out\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.577 ns" { Din[3] de:comb_4|out[3] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.218 ns ( 18.95 % ) " "Info: Total cell delay = 1.218 ns ( 18.95 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.211 ns ( 81.05 % ) " "Info: Total interconnect delay = 5.211 ns ( 81.05 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.429 ns" { Din[3] de:comb_4|out[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.429 ns" { Din[3] Din[3]~combout de:comb_4|out[3] } { 0.000ns 0.000ns 5.211ns } { 0.000ns 0.852ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.374 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.374 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 72 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.726 ns) + CELL(0.537 ns) 2.374 ns de:comb_4\|out\[3\] 3 REG LCFF_X19_Y13_N1 1 " "Info: 3: + IC(0.726 ns) + CELL(0.537 ns) = 2.374 ns; Loc. = LCFF_X19_Y13_N1; Fanout = 1; REG Node = 'de:comb_4\|out\[3\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.263 ns" { clk~clkctrl de:comb_4|out[3] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.28 % ) " "Info: Total cell delay = 1.526 ns ( 64.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.848 ns ( 35.72 % ) " "Info: Total interconnect delay = 0.848 ns ( 35.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.374 ns" { clk clk~clkctrl de:comb_4|out[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.374 ns" { clk clk~combout clk~clkctrl de:comb_4|out[3] } { 0.000ns 0.000ns 0.122ns 0.726ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.429 ns" { Din[3] de:comb_4|out[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.429 ns" { Din[3] Din[3]~combout de:comb_4|out[3] } { 0.000ns 0.000ns 5.211ns } { 0.000ns 0.852ns 0.366ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.374 ns" { clk clk~clkctrl de:comb_4|out[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.374 ns" { clk clk~combout clk~clkctrl de:comb_4|out[3] } { 0.000ns 0.000ns 0.122ns 0.726ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk Dout\[5\] de:comb_12\|out\[5\] 7.343 ns register " "Info: tco from clock \"clk\" to destination pin \"Dout\[5\]\" through register \"de:comb_12\|out\[5\]\" is 7.343 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.361 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 72 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.713 ns) + CELL(0.537 ns) 2.361 ns de:comb_12\|out\[5\] 3 REG LCFF_X19_Y9_N13 1 " "Info: 3: + IC(0.713 ns) + CELL(0.537 ns) = 2.361 ns; Loc. = LCFF_X19_Y9_N13; Fanout = 1; REG Node = 'de:comb_12\|out\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.250 ns" { clk~clkctrl de:comb_12|out[5] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.63 % ) " "Info: Total cell delay = 1.526 ns ( 64.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.835 ns ( 35.37 % ) " "Info: Total interconnect delay = 0.835 ns ( 35.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.361 ns" { clk clk~clkctrl de:comb_12|out[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.361 ns" { clk clk~combout clk~clkctrl de:comb_12|out[5] } { 0.000ns 0.000ns 0.122ns 0.713ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.732 ns + Longest register pin " "Info: + Longest register to pin delay is 4.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns de:comb_12\|out\[5\] 1 REG LCFF_X19_Y9_N13 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y9_N13; Fanout = 1; REG Node = 'de:comb_12\|out\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { de:comb_12|out[5] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.080 ns) + CELL(2.652 ns) 4.732 ns Dout\[5\] 2 PIN PIN_26 0 " "Info: 2: + IC(2.080 ns) + CELL(2.652 ns) = 4.732 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'Dout\[5\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.732 ns" { de:comb_12|out[5] Dout[5] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.652 ns ( 56.04 % ) " "Info: Total cell delay = 2.652 ns ( 56.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.080 ns ( 43.96 % ) " "Info: Total interconnect delay = 2.080 ns ( 43.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.732 ns" { de:comb_12|out[5] Dout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.732 ns" { de:comb_12|out[5] Dout[5] } { 0.000ns 2.080ns } { 0.000ns 2.652ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.361 ns" { clk clk~clkctrl de:comb_12|out[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.361 ns" { clk clk~combout clk~clkctrl de:comb_12|out[5] } { 0.000ns 0.000ns 0.122ns 0.713ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.732 ns" { de:comb_12|out[5] Dout[5] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.732 ns" { de:comb_12|out[5] Dout[5] } { 0.000ns 2.080ns } { 0.000ns 2.652ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "de:comb_4\|out\[7\] Din\[7\] clk 0.250 ns register " "Info: th for register \"de:comb_4\|out\[7\]\" (data pin = \"Din\[7\]\", clock pin = \"clk\") is 0.250 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.347 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.347 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk~clkctrl 2 COMB CLKCTRL_G2 72 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk clk~clkctrl } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.699 ns) + CELL(0.537 ns) 2.347 ns de:comb_4\|out\[7\] 3 REG LCFF_X15_Y8_N29 1 " "Info: 3: + IC(0.699 ns) + CELL(0.537 ns) = 2.347 ns; Loc. = LCFF_X15_Y8_N29; Fanout = 1; REG Node = 'de:comb_4\|out\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.236 ns" { clk~clkctrl de:comb_4|out[7] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 65.02 % ) " "Info: Total cell delay = 1.526 ns ( 65.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.821 ns ( 34.98 % ) " "Info: Total interconnect delay = 0.821 ns ( 34.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.347 ns" { clk clk~clkctrl de:comb_4|out[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.347 ns" { clk clk~combout clk~clkctrl de:comb_4|out[7] } { 0.000ns 0.000ns 0.122ns 0.699ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.363 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns Din\[7\] 1 PIN PIN_88 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'Din\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { Din[7] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.998 ns) + CELL(0.366 ns) 2.363 ns de:comb_4\|out\[7\] 2 REG LCFF_X15_Y8_N29 1 " "Info: 2: + IC(0.998 ns) + CELL(0.366 ns) = 2.363 ns; Loc. = LCFF_X15_Y8_N29; Fanout = 1; REG Node = 'de:comb_4\|out\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.364 ns" { Din[7] de:comb_4|out[7] } "NODE_NAME" } } { "delay.v" "" { Text "C:/Documents and Settings/user/桌面/delay/delay/delay.v" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.365 ns ( 57.77 % ) " "Info: Total cell delay = 1.365 ns ( 57.77 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.998 ns ( 42.23 % ) " "Info: Total interconnect delay = 0.998 ns ( 42.23 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.363 ns" { Din[7] de:comb_4|out[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.363 ns" { Din[7] Din[7]~combout de:comb_4|out[7] } { 0.000ns 0.000ns 0.998ns } { 0.000ns 0.999ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.347 ns" { clk clk~clkctrl de:comb_4|out[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.347 ns" { clk clk~combout clk~clkctrl de:comb_4|out[7] } { 0.000ns 0.000ns 0.122ns 0.699ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.363 ns" { Din[7] de:comb_4|out[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.363 ns" { Din[7] Din[7]~combout de:comb_4|out[7] } { 0.000ns 0.000ns 0.998ns } { 0.000ns 0.999ns 0.366ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}