delay.tan.rpt

在Quartus下使用D触发器来加入延迟

+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+--------+------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From   ; To               ; To Clock ;
+---------------+-------------+-----------+--------+------------------+----------+
; N/A           ; None        ; 0.250 ns  ; Din[7] ; de:comb_4|out[7] ; clk      ;
; N/A           ; None        ; -2.913 ns ; Din[4] ; de:comb_4|out[4] ; clk      ;
; N/A           ; None        ; -2.930 ns ; Din[0] ; de:comb_4|out[0] ; clk      ;
; N/A           ; None        ; -3.150 ns ; Din[1] ; de:comb_4|out[1] ; clk      ;
; N/A           ; None        ; -3.400 ns ; Din[2] ; de:comb_4|out[2] ; clk      ;
; N/A           ; None        ; -3.641 ns ; Din[6] ; de:comb_4|out[6] ; clk      ;
; N/A           ; None        ; -3.731 ns ; Din[5] ; de:comb_4|out[5] ; clk      ;
; N/A           ; None        ; -3.789 ns ; Din[3] ; de:comb_4|out[3] ; clk      ;
+---------------+-------------+-----------+--------+------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Fri Oct 12 13:46:07 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off delay -c delay --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" Internal fmax is restricted to 420.17 MHz between source register "de:comb_11|out[2]" and destination register "de:comb_12|out[2]"
    Info: fmax restricted to clock pin edge rate 2.38 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 0.542 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X1_Y1_N23; Fanout = 1; REG Node = 'de:comb_11|out[2]'
            Info: 2: + IC(0.309 ns) + CELL(0.149 ns) = 0.458 ns; Loc. = LCCOMB_X1_Y1_N0; Fanout = 1; COMB Node = 'de:comb_12|out[2]~feeder'
            Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.542 ns; Loc. = LCFF_X1_Y1_N1; Fanout = 1; REG Node = 'de:comb_12|out[2]'
            Info: Total cell delay = 0.233 ns ( 42.99 % )
            Info: Total interconnect delay = 0.309 ns ( 57.01 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clk" to destination register is 2.357 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N1; Fanout = 1; REG Node = 'de:comb_12|out[2]'
                Info: Total cell delay = 1.526 ns ( 64.74 % )
                Info: Total interconnect delay = 0.831 ns ( 35.26 % )
            Info: - Longest clock path from clock "clk" to source register is 2.357 ns
                Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'
                Info: 3: + IC(0.709 ns) + CELL(0.537 ns) = 2.357 ns; Loc. = LCFF_X1_Y1_N23; Fanout = 1; REG Node = 'de:comb_11|out[2]'
                Info: Total cell delay = 1.526 ns ( 64.74 % )
                Info: Total interconnect delay = 0.831 ns ( 35.26 % )
        Info: + Micro clock to output delay of source is 0.250 ns
        Info: + Micro setup delay of destination is -0.036 ns
Info: tsu for register "de:comb_4|out[3]" (data pin = "Din[3]", clock pin = "clk") is 4.019 ns
    Info: + Longest pin to register delay is 6.429 ns
        Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_103; Fanout = 1; PIN Node = 'Din[3]'
        Info: 2: + IC(5.211 ns) + CELL(0.366 ns) = 6.429 ns; Loc. = LCFF_X19_Y13_N1; Fanout = 1; REG Node = 'de:comb_4|out[3]'
        Info: Total cell delay = 1.218 ns ( 18.95 % )
        Info: Total interconnect delay = 5.211 ns ( 81.05 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.374 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.726 ns) + CELL(0.537 ns) = 2.374 ns; Loc. = LCFF_X19_Y13_N1; Fanout = 1; REG Node = 'de:comb_4|out[3]'
        Info: Total cell delay = 1.526 ns ( 64.28 % )
        Info: Total interconnect delay = 0.848 ns ( 35.72 % )
Info: tco from clock "clk" to destination pin "Dout[5]" through register "de:comb_12|out[5]" is 7.343 ns
    Info: + Longest clock path from clock "clk" to source register is 2.361 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.713 ns) + CELL(0.537 ns) = 2.361 ns; Loc. = LCFF_X19_Y9_N13; Fanout = 1; REG Node = 'de:comb_12|out[5]'
        Info: Total cell delay = 1.526 ns ( 64.63 % )
        Info: Total interconnect delay = 0.835 ns ( 35.37 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.732 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y9_N13; Fanout = 1; REG Node = 'de:comb_12|out[5]'
        Info: 2: + IC(2.080 ns) + CELL(2.652 ns) = 4.732 ns; Loc. = PIN_26; Fanout = 0; PIN Node = 'Dout[5]'
        Info: Total cell delay = 2.652 ns ( 56.04 % )
        Info: Total interconnect delay = 2.080 ns ( 43.96 % )
Info: th for register "de:comb_4|out[7]" (data pin = "Din[7]", clock pin = "clk") is 0.250 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.347 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 72; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.699 ns) + CELL(0.537 ns) = 2.347 ns; Loc. = LCFF_X15_Y8_N29; Fanout = 1; REG Node = 'de:comb_4|out[7]'
        Info: Total cell delay = 1.526 ns ( 65.02 % )
        Info: Total interconnect delay = 0.821 ns ( 34.98 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 2.363 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_88; Fanout = 1; PIN Node = 'Din[7]'
        Info: 2: + IC(0.998 ns) + CELL(0.366 ns) = 2.363 ns; Loc. = LCFF_X15_Y8_N29; Fanout = 1; REG Node = 'de:comb_4|out[7]'
        Info: Total cell delay = 1.365 ns ( 57.77 % )
        Info: Total interconnect delay = 0.998 ns ( 42.23 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Fri Oct 12 13:46:07 2007
    Info: Elapsed time: 00:00:01