stm8s105c_s.h

STM8S105S4程序

/* TIM1 Capture/Compare mode register 1 */
DEF_8BIT_REG_AT(TIM1_CCMR1,0x5258);

/* TIM1 Capture/Compare mode register 2 */
DEF_8BIT_REG_AT(TIM1_CCMR2,0x5259);

/* TIM1 Capture/Compare mode register 3 */
DEF_8BIT_REG_AT(TIM1_CCMR3,0x525a);

/* TIM1 Capture/Compare mode register 4 */
DEF_8BIT_REG_AT(TIM1_CCMR4,0x525b);

/* TIM1 Capture/Compare enable register 1 */
DEF_8BIT_REG_AT(TIM1_CCER1,0x525c);

/* TIM1 Capture/Compare enable register 2 */
DEF_8BIT_REG_AT(TIM1_CCER2,0x525d);

/* TIM1 Counter */
DEF_16BIT_REG_AT(TIM1_CNTR,0x525e);
/* Data bits High */
DEF_8BIT_REG_AT(TIM1_CNTRH,0x525e);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM1_CNTRL,0x525f);

/* TIM1 Prescaler register */
DEF_16BIT_REG_AT(TIM1_PSCR,0x5260);
/* Data bits High */
DEF_8BIT_REG_AT(TIM1_PSCRH,0x5260);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM1_PSCRL,0x5261);

/* TIM1 Auto-reload register */
DEF_16BIT_REG_AT(TIM1_ARR,0x5262);
/* Data bits High */
DEF_8BIT_REG_AT(TIM1_ARRH,0x5262);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM1_ARRL,0x5263);

/* TIM1 Repetition counter register */
DEF_8BIT_REG_AT(TIM1_RCR,0x5264);

/* TIM1 Capture/Compare register 1 */
DEF_16BIT_REG_AT(TIM1_CCR1,0x5265);
/* Data bits High */
DEF_8BIT_REG_AT(TIM1_CCR1H,0x5265);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM1_CCR1L,0x5266);

/* TIM1 Capture/Compare register 2 */
DEF_16BIT_REG_AT(TIM1_CCR2,0x5267);
/* Data bits High */
DEF_8BIT_REG_AT(TIM1_CCR2H,0x5267);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM1_CCR2L,0x5268);

/* TIM1 Capture/Compare register 3 */
DEF_16BIT_REG_AT(TIM1_CCR3,0x5269);
/* Data bits High */
DEF_8BIT_REG_AT(TIM1_CCR3H,0x5269);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM1_CCR3L,0x526a);

/* TIM1 Capture/Compare register 4 */
DEF_16BIT_REG_AT(TIM1_CCR4,0x526b);
/* Data bits High */
DEF_8BIT_REG_AT(TIM1_CCR4H,0x526b);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM1_CCR4L,0x526c);

/* TIM1 Break register */
DEF_8BIT_REG_AT(TIM1_BKR,0x526d);

/* TIM1 Dead-time register */
DEF_8BIT_REG_AT(TIM1_DTR,0x526e);

/* TIM1 Output idle state register */
DEF_8BIT_REG_AT(TIM1_OISR,0x526f);

/* 16-Bit Timer 2 (TIM2) */
/*****************************************************************/

/* TIM2 Control register 1 */
DEF_8BIT_REG_AT(TIM2_CR1,0x5300);

/* TIM2 Interrupt enable register */
DEF_8BIT_REG_AT(TIM2_IER,0x5301);

/* TIM2 Status register 1 */
DEF_8BIT_REG_AT(TIM2_SR1,0x5302);

/* TIM2 Status register 2 */
DEF_8BIT_REG_AT(TIM2_SR2,0x5303);

/* TIM2 Event Generation register */
DEF_8BIT_REG_AT(TIM2_EGR,0x5304);

/* TIM2 Capture/Compare mode register 1 */
DEF_8BIT_REG_AT(TIM2_CCMR1,0x5305);

/* TIM2 Capture/Compare mode register 2 */
DEF_8BIT_REG_AT(TIM2_CCMR2,0x5306);

/* TIM2 Capture/Compare mode register 3 */
DEF_8BIT_REG_AT(TIM2_CCMR3,0x5307);

/* TIM2 Capture/Compare enable register 1 */
DEF_8BIT_REG_AT(TIM2_CCER1,0x5308);

/* TIM2 Capture/Compare enable register 2 */
DEF_8BIT_REG_AT(TIM2_CCER2,0x5309);

/* TIM2 Counter */
DEF_16BIT_REG_AT(TIM2_CNTR,0x530a);
/* Data bits High */
DEF_8BIT_REG_AT(TIM2_CNTRH,0x530a);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM2_CNTRL,0x530b);

/* TIM2 Prescaler register */
DEF_8BIT_REG_AT(TIM2_PSCR,0x530c);

/* TIM2 Auto-reload register */
DEF_16BIT_REG_AT(TIM2_ARR,0x530d);
/* Data bits High */
DEF_8BIT_REG_AT(TIM2_ARRH,0x530d);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM2_ARRL,0x530e);

/* TIM2 Capture/Compare register 1 */
DEF_16BIT_REG_AT(TIM2_CCR1,0x530f);
/* Data bits High */
DEF_8BIT_REG_AT(TIM2_CCR1H,0x530f);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM2_CCR1L,0x5310);

/* TIM2 Capture/Compare register 2 */
DEF_16BIT_REG_AT(TIM2_CCR2,0x5311);
/* Data bits High */
DEF_8BIT_REG_AT(TIM2_CCR2H,0x5311);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM2_CCR2L,0x5312);

/* TIM2 Capture/Compare register 3 */
DEF_16BIT_REG_AT(TIM2_CCR3,0x5313);
/* Data bits High */
DEF_8BIT_REG_AT(TIM2_CCR3H,0x5313);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM2_CCR3L,0x5314);

/* 16-Bit Timer 3 (TIM3) */
/*****************************************************************/

/* TIM3 Control register 1 */
DEF_8BIT_REG_AT(TIM3_CR1,0x5320);

/* TIM3 Interrupt enable register */
DEF_8BIT_REG_AT(TIM3_IER,0x5321);

/* TIM3 Status register 1 */
DEF_8BIT_REG_AT(TIM3_SR1,0x5322);

/* TIM3 Status register 2 */
DEF_8BIT_REG_AT(TIM3_SR2,0x5323);

/* TIM3 Event Generation register */
DEF_8BIT_REG_AT(TIM3_EGR,0x5324);

/* TIM3 Capture/Compare mode register 1 */
DEF_8BIT_REG_AT(TIM3_CCMR1,0x5325);

/* TIM3 Capture/Compare mode register 2 */
DEF_8BIT_REG_AT(TIM3_CCMR2,0x5326);

/* TIM3 Capture/Compare enable register 1 */
DEF_8BIT_REG_AT(TIM3_CCER1,0x5327);

/* TIM3 Counter */
DEF_16BIT_REG_AT(TIM3_CNTR,0x5328);
/* Data bits High */
DEF_8BIT_REG_AT(TIM3_CNTRH,0x5328);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM3_CNTRL,0x5329);

/* TIM3 Prescaler register */
DEF_8BIT_REG_AT(TIM3_PSCR,0x532a);

/* TIM3 Auto-reload register */
DEF_16BIT_REG_AT(TIM3_ARR,0x532b);
/* Data bits High */
DEF_8BIT_REG_AT(TIM3_ARRH,0x532b);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM3_ARRL,0x532c);

/* TIM3 Capture/Compare register */
DEF_16BIT_REG_AT(TIM3_CCR1,0x532d);
/* Data bits High */
DEF_8BIT_REG_AT(TIM3_CCR1H,0x532d);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM3_CCR1L,0x532e);

/* TIM3 Capture/Compare register */
DEF_16BIT_REG_AT(TIM3_CCR2,0x532f);
/* Data bits High */
DEF_8BIT_REG_AT(TIM3_CCR2H,0x532f);
/* Data bits Low */
DEF_8BIT_REG_AT(TIM3_CCR2L,0x5330);

/* 8-Bit  Timer 4 (TIM4) */
/*****************************************************************/

/* TIM4 Control register 1 */
DEF_8BIT_REG_AT(TIM4_CR1,0x5340);

/* TIM4 Interrupt enable register */
DEF_8BIT_REG_AT(TIM4_IER,0x5341);

/* TIM4 Status register */
DEF_8BIT_REG_AT(TIM4_SR,0x5342);

/* TIM4 Event Generation register */
DEF_8BIT_REG_AT(TIM4_EGR,0x5343);

/* TIM4 Counter */
DEF_8BIT_REG_AT(TIM4_CNTR,0x5344);

/* TIM4 Prescaler register */
DEF_8BIT_REG_AT(TIM4_PSCR,0x5345);

/* TIM4 Auto-reload register */
DEF_8BIT_REG_AT(TIM4_ARR,0x5346);

/* 10-Bit A/D Converter (ADC1) */
/*****************************************************************/

/* ADC Data buffer Register 0 */
DEF_16BIT_REG_AT(ADC_DB0R,0x53e0);
/* Data Buffer register 0 High */
DEF_8BIT_REG_AT(ADC_DB0RH,0x53e0);
/* Data Buffer register 0 Low */
DEF_8BIT_REG_AT(ADC_DB0RL,0x53e1);

/* ADC Data buffer Register 1 */
DEF_16BIT_REG_AT(ADC_DB1R,0x53e2);
/* Data Buffer register 1 High */
DEF_8BIT_REG_AT(ADC_DB1RH,0x53e2);
/* Data Buffer register 1 Low */
DEF_8BIT_REG_AT(ADC_DB1RL,0x53e3);

/* ADC Data buffer Register 2 */
DEF_16BIT_REG_AT(ADC_DB2R,0x53e4);
/* Data Buffer register 2 High */
DEF_8BIT_REG_AT(ADC_DB2RH,0x53e4);
/* Data Buffer register 2 Low */
DEF_8BIT_REG_AT(ADC_DB2RL,0x53e5);

/* ADC Data buffer Register 3 */
DEF_16BIT_REG_AT(ADC_DB3R,0x53e6);
/* Data Buffer register 3 High */
DEF_8BIT_REG_AT(ADC_DB3RH,0x53e6);
/* Data Buffer register 3 Low */
DEF_8BIT_REG_AT(ADC_DB3RL,0x53e7);

/* ADC Data buffer Register 4 */
DEF_16BIT_REG_AT(ADC_DB4R,0x53e8);
/* Data Buffer register 4 High */
DEF_8BIT_REG_AT(ADC_DB4RH,0x53e8);
/* Data Buffer register 4 Low */
DEF_8BIT_REG_AT(ADC_DB4RL,0x53e9);

/* ADC Data buffer Register 5 */
DEF_16BIT_REG_AT(ADC_DB5R,0x53ea);
/* Data Buffer register 5 High */
DEF_8BIT_REG_AT(ADC_DB5RH,0x53ea);
/* Data Buffer register 5 Low */
DEF_8BIT_REG_AT(ADC_DB5RL,0x53eb);

/* ADC Data buffer Register 6 */
DEF_16BIT_REG_AT(ADC_DB6R,0x53ec);
/* Data Buffer register 6 High */
DEF_8BIT_REG_AT(ADC_DB6RH,0x53ec);
/* Data Buffer register 6 Low */
DEF_8BIT_REG_AT(ADC_DB6RL,0x53ed);

/* ADC Data buffer Register 7 */
DEF_16BIT_REG_AT(ADC_DB7R,0x53ee);
/* Data Buffer register 7 High */
DEF_8BIT_REG_AT(ADC_DB7RH,0x53ee);
/* Data Buffer register 7 Low */
DEF_8BIT_REG_AT(ADC_DB7RL,0x53ef);

/* ADC Data buffer Register 8 */
DEF_16BIT_REG_AT(ADC_DB8R,0x53f0);
/* Data Buffer register 8 High */
DEF_8BIT_REG_AT(ADC_DB8RH,0x53f0);
/* Data Buffer register 8 Low */
DEF_8BIT_REG_AT(ADC_DB8RL,0x53f1);

/* ADC Data buffer Register 9 */
DEF_16BIT_REG_AT(ADC_DB9R,0x53f2);
/* Data Buffer register 9 High */
DEF_8BIT_REG_AT(ADC_DB9RH,0x53f2);
/* Data Buffer register 9 Low */
DEF_8BIT_REG_AT(ADC_DB9RL,0x53f3);

/* ADC Control/Status Register */
DEF_8BIT_REG_AT(ADC_CSR,0x5400);

/* ADC Configuration Register 1 */
DEF_8BIT_REG_AT(ADC_CR1,0x5401);

/* ADC Configuration Register 2 */
DEF_8BIT_REG_AT(ADC_CR2,0x5402);

/* ADC Configuration Register 3 */
DEF_8BIT_REG_AT(ADC_CR3,0x5403);

/* ADC Data Register */
DEF_16BIT_REG_AT(ADC_DR,0x5404);
/* Data bits High */
DEF_8BIT_REG_AT(ADC_DRH,0x5404);
/* Data bits Low */
DEF_8BIT_REG_AT(ADC_DRL,0x5405);

/* ADC Schmitt Trigger Disable Register */
DEF_16BIT_REG_AT(ADC_TDR,0x5406);
/* Schmitt trigger disable High */
DEF_8BIT_REG_AT(ADC_TDRH,0x5406);
/* Schmitt trigger disable Low */
DEF_8BIT_REG_AT(ADC_TDRL,0x5407);

/* ADC High Threshold Register */
DEF_16BIT_REG_AT(ADC_HTR,0x5408);
/* High Threshold Register High */
DEF_8BIT_REG_AT(ADC_HTRH,0x5408);
/* High Threshold Register Low */
DEF_8BIT_REG_AT(ADC_HTRL,0x5409);

/* ADC Low Threshold Register */
DEF_16BIT_REG_AT(ADC_LTR,0x540a);
/* Low Threshold Register High */
DEF_8BIT_REG_AT(ADC_LTRH,0x540a);
/* Low Threshold Register Low */
DEF_8BIT_REG_AT(ADC_LTRL,0x540b);

/* ADC Analog Watchdog Status Register */
DEF_16BIT_REG_AT(ADC_AWSR,0x540c);
/* Analog Watchdog Status register High */
DEF_8BIT_REG_AT(ADC_AWSRH,0x540c);
/* Analog Watchdog Status register Low */
DEF_8BIT_REG_AT(ADC_AWSRL,0x540d);

/* ADC Analog Watchdog Control Register */
DEF_16BIT_REG_AT(ADC_AWCR,0x540e);
/* Analog Watchdog Control register High */
DEF_8BIT_REG_AT(ADC_AWCRH,0x540e);
/* Analog Watchdog Control register Low */
DEF_8BIT_REG_AT(ADC_AWCRL,0x540f);

/*  Global configuration register (CFG) */
/*****************************************************************/

/* CFG Global configuration register */
DEF_8BIT_REG_AT(CFG_GCR,0x7f60);

/* Interrupt Software Priority Register (ITC) */
/*****************************************************************/

/* Interrupt Software priority register 1 */
DEF_8BIT_REG_AT(ITC_SPR1,0x7f70);

/* Interrupt Software priority register 2 */
DEF_8BIT_REG_AT(ITC_SPR2,0x7f71);

/* Interrupt Software priority register 3 */
DEF_8BIT_REG_AT(ITC_SPR3,0x7f72);

/* Interrupt Software priority register 4 */
DEF_8BIT_REG_AT(ITC_SPR4,0x7f73);

/* Interrupt Software priority register 5 */
DEF_8BIT_REG_AT(ITC_SPR5,0x7f74);

/* Interrupt Software priority register 6 */
DEF_8BIT_REG_AT(ITC_SPR6,0x7f75);

/* Interrupt Software priority register 7 */
DEF_8BIT_REG_AT(ITC_SPR7,0x7f76);

#endif /* __STM8S105C_S__ */