📄 main.lst
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437 000000 EXTERN ADC_DB3RH.w ; Data Buffer register 3 High
438
439 000000 EXTERN ADC_DB3RL.w ; Data Buffer register 3 Low
440
441 000000 EXTERN ADC_DB4RH.w ; Data Buffer register 4 High
442
443 000000 EXTERN ADC_DB4RL.w ; Data Buffer register 4 Low
444
445 000000 EXTERN ADC_DB5RH.w ; Data Buffer register 5 High
446
447 000000 EXTERN ADC_DB5RL.w ; Data Buffer register 5 Low
448
449 000000 EXTERN ADC_DB6RH.w ; Data Buffer register 6 High
450
451 000000 EXTERN ADC_DB6RL.w ; Data Buffer register 6 Low
452
453 000000 EXTERN ADC_DB7RH.w ; Data Buffer register 7 High
454
455 000000 EXTERN ADC_DB7RL.w ; Data Buffer register 7 Low
456
457 000000 EXTERN ADC_DB8RH.w ; Data Buffer register 8 High
458
459 000000 EXTERN ADC_DB8RL.w ; Data Buffer register 8 Low
460
461 000000 EXTERN ADC_DB9RH.w ; Data Buffer register 9 High
462
STMicroelectronics list file postprocessor v1.01 (C)2009-2012 Thu May 03 11:07:40 2012
Page 11 Assembler
f:\stm8\stm8实验\第五次课\复件 ad单次\main.asm
463 000000 EXTERN ADC_DB9RL.w ; Data Buffer register 9 Low
464
465 000000 EXTERN ADC_CSR.w ; ADC Control/Status Register
466
467 000000 EXTERN ADC_CR1.w ; ADC Configuration Register 1
468
469 000000 EXTERN ADC_CR2.w ; ADC Configuration Register 2
470
471 000000 EXTERN ADC_CR3.w ; ADC Configuration Register 3
472
473 000000 EXTERN ADC_DRH.w ; Data bits High
474
475 000000 EXTERN ADC_DRL.w ; Data bits Low
476
477 000000 EXTERN ADC_TDRH.w ; Schmitt trigger disable High
478
479 000000 EXTERN ADC_TDRL.w ; Schmitt trigger disable Low
480
481 000000 EXTERN ADC_HTRH.w ; High Threshold Register High
482
483 000000 EXTERN ADC_HTRL.w ; High Threshold Register Low
484
485 000000 EXTERN ADC_LTRH.w ; Low Threshold Register High
486
487 000000 EXTERN ADC_LTRL.w ; Low Threshold Register Low
488
489 000000 EXTERN ADC_AWSRH.w ; Analog Watchdog Status
;register High
490
491 000000 EXTERN ADC_AWSRL.w ; Analog Watchdog Status
;register Low
492
493 000000 EXTERN ADC_AWCRH.w ; Analog Watchdog Control
;register High
494
495 000000 EXTERN ADC_AWCRL.w ; Analog Watchdog Control
;register Low
496
497 ; Global configuration register (CFG)
498 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;
499
500 000000 EXTERN CFG_GCR.w ; CFG Global configuration
;register
501
502 ; Interrupt Software Priority Register (ITC)
503 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;
504
505 000000 EXTERN ITC_SPR1.w ; Interrupt Software priority
;register 1
506
507 000000 EXTERN ITC_SPR2.w ; Interrupt Software priority
;register 2
508
509 000000 EXTERN ITC_SPR3.w ; Interrupt Software priority
;register 3
STMicroelectronics list file postprocessor v1.01 (C)2009-2012 Thu May 03 11:07:40 2012
Page 12 Assembler
f:\stm8\stm8实验\第五次课\复件 ad单次\main.asm
510
511 000000 EXTERN ITC_SPR4.w ; Interrupt Software priority
;register 4
512
513 000000 EXTERN ITC_SPR5.w ; Interrupt Software priority
;register 5
514
515 000000 EXTERN ITC_SPR6.w ; Interrupt Software priority
;register 6
516
517 000000 EXTERN ITC_SPR7.w ; Interrupt Software priority
;register 7
518
519 000000 #endif ; __STM8S105C_S__
<END_OF_INCLUSION>
5 segment 'ram0'
6 000000 couter ds.b 1
7 000001 vol1 ds.b 1
8 000002 vol2 ds.b 1
9 000003 vol3 ds.b 1
10 segment 'rom'
11 main.l
12 ; initialize SP
13 008080 AE07FF ldw X,#stack_end
14 008083 94 ldw SP,X
15
16 008084 #ifdef 1
17 ; clear RAM0
18 000000 ram0_start.b EQU $0
19 0000FF ram0_end.b EQU $FF
20 008084 AE0000 ldw X,#ram0_start
21 clear_ram0.l
22 008087 7F clr (X)
23 008088 5C incw X
24 008089 A300FF cpw X,#ram0_end
25 00808C 23F9 jrule clear_ram0
26 00808E #endif
27
28 00808E #ifdef 1
29 ; clear RAM1
30 000100 ram1_start.w EQU $100
31 0005FF ram1_end.w EQU $5FF
32 00808E AE0100 ldw X,#ram1_start
33 clear_ram1.l
34 008091 7F clr (X)
35 008092 5C incw X
36 008093 A305FF cpw X,#ram1_end
37 008096 23F9 jrule clear_ram1
38 008098 #endif
39
40 ; clear stack
41 000600 stack_start.w EQU $600
42 0007FF stack_end.w EQU $7FF
43 008098 AE0600 ldw X,#stack_start
44 clear_stack.l
45 00809B 7F clr (X)
46 00809C 5C incw X
47 00809D A307FF cpw X,#stack_end
STMicroelectronics list file postprocessor v1.01 (C)2009-2012 Thu May 03 11:07:40 2012
Page 13 Assembler
f:\stm8\stm8实验\第五次课\复件 ad单次\main.asm
48 0080A0 23F9 jrule clear_stack
49
50 0080A2 intel
51 ;初始化PB,推挽输出,用于数码管段驱动；
52 0080A2 35FF5007 mov PB_DDR,#0ffh
53 0080A6 35FF5008 mov PB_CR1,#0ffh
54 0080AA 35005009 mov PB_CR2,#0
55 ;初始化PA,推挽输出,用于数码管位驱动；
56 0080AE 35FF5002 mov PA_DDR,#0ffh
57 0080B2 35FF5003 mov PA_CR1,#0ffh
58 0080B6 35005004 mov PA_CR2,#0
59 0080BA 35FF5000 mov PA_ODR,#0ffh
60
61
62 0080BE 35005244 mov UART2_CR1,#0
63 0080C2 35005245 mov UART2_CR2,#0
64 0080C6 35005246 mov UART2_CR3,#0
65 0080CA 35005243 mov UART2_BRR2,#0
66 0080CE 350D5242 mov UART2_BRR1,#0dh
67 0080D2 350C5245 mov UART2_CR2,#0ch
68
69 0080D6 35005402 mov ADC_CR2,#0 ; A/D结果数据左对齐
70
71 0080DA 5500005401 mov ADC_CR1,0 ; ADC时钟=主时钟/2=1MHZ
72
73 ; ADC转换模式=单次
74
75 ; 禁止ADC转换
76
77 0080DF 35085400 mov ADC_CSR,#8 ; 选择通道0
78
79 0080E3 35015406 mov ADC_TDRH,#1
80
81
82 0080E7 72105401 bset ADC_CR1,#0
83 0080EB A664 ld a,#100
84 WAIT_ADC_ON.L
85 0080ED 4A dec a
86 0080EE 26FD jrne WAIT_ADC_ON ;
;延时一段时间，至少7uS，保证ADC⌨️ 快捷键说明
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