📄 main.lsr
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437 000000 EXTERN ADC_DB3RH.w ; Data Buffer register 3 High
438
439 000000 EXTERN ADC_DB3RL.w ; Data Buffer register 3 Low
440
441 000000 EXTERN ADC_DB4RH.w ; Data Buffer register 4 High
442
443 000000 EXTERN ADC_DB4RL.w ; Data Buffer register 4 Low
444
445 000000 EXTERN ADC_DB5RH.w ; Data Buffer register 5 High
446
447 000000 EXTERN ADC_DB5RL.w ; Data Buffer register 5 Low
448
449 000000 EXTERN ADC_DB6RH.w ; Data Buffer register 6 High
450
451 000000 EXTERN ADC_DB6RL.w ; Data Buffer register 6 Low
452
453 000000 EXTERN ADC_DB7RH.w ; Data Buffer register 7 High
454
455 000000 EXTERN ADC_DB7RL.w ; Data Buffer register 7 Low
456
457 000000 EXTERN ADC_DB8RH.w ; Data Buffer register 8 High
458
459 000000 EXTERN ADC_DB8RL.w ; Data Buffer register 8 Low
460
461 000000 EXTERN ADC_DB9RH.w ; Data Buffer register 9 High
462
STMicroelectronics assembler v4.52 (C)1987-2011 Tue May 31 13:32:51 2011
Page 11 Assembler
f:\stm8\stm8实验\第五次课\复件 (2) ad单次\main.asm
463 000000 EXTERN ADC_DB9RL.w ; Data Buffer register 9 Low
464
465 000000 EXTERN ADC_CSR.w ; ADC Control/Status Register
466
467 000000 EXTERN ADC_CR1.w ; ADC Configuration Register 1
468
469 000000 EXTERN ADC_CR2.w ; ADC Configuration Register 2
470
471 000000 EXTERN ADC_CR3.w ; ADC Configuration Register 3
472
473 000000 EXTERN ADC_DRH.w ; Data bits High
474
475 000000 EXTERN ADC_DRL.w ; Data bits Low
476
477 000000 EXTERN ADC_TDRH.w ; Schmitt trigger disable High
478
479 000000 EXTERN ADC_TDRL.w ; Schmitt trigger disable Low
480
481 000000 EXTERN ADC_HTRH.w ; High Threshold Register High
482
483 000000 EXTERN ADC_HTRL.w ; High Threshold Register Low
484
485 000000 EXTERN ADC_LTRH.w ; Low Threshold Register High
486
487 000000 EXTERN ADC_LTRL.w ; Low Threshold Register Low
488
489 000000 EXTERN ADC_AWSRH.w ; Analog Watchdog Status
;register High
490
491 000000 EXTERN ADC_AWSRL.w ; Analog Watchdog Status
;register Low
492
493 000000 EXTERN ADC_AWCRH.w ; Analog Watchdog Control
;register High
494
495 000000 EXTERN ADC_AWCRL.w ; Analog Watchdog Control
;register Low
496
497 ; Global configuration register (CFG)
498 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;
499
500 000000 EXTERN CFG_GCR.w ; CFG Global configuration
;register
501
502 ; Interrupt Software Priority Register (ITC)
503 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;
504
505 000000 EXTERN ITC_SPR1.w ; Interrupt Software priority
;register 1
506
507 000000 EXTERN ITC_SPR2.w ; Interrupt Software priority
;register 2
508
509 000000 EXTERN ITC_SPR3.w ; Interrupt Software priority
;register 3
STMicroelectronics assembler v4.52 (C)1987-2011 Tue May 31 13:32:51 2011
Page 12 Assembler
f:\stm8\stm8实验\第五次课\复件 (2) ad单次\main.asm
510
511 000000 EXTERN ITC_SPR4.w ; Interrupt Software priority
;register 4
512
513 000000 EXTERN ITC_SPR5.w ; Interrupt Software priority
;register 5
514
515 000000 EXTERN ITC_SPR6.w ; Interrupt Software priority
;register 6
516
517 000000 EXTERN ITC_SPR7.w ; Interrupt Software priority
;register 7
518
519 000000 #endif ; __STM8S105C_S__
<END_OF_INCLUSION>
5 segment 'ram0'
6 000000 couter ds.b 1
7 000001 vol1 ds.b 1
8 000002 vol2 ds.b 1
9 000003 vol3 ds.b 1
10
11 000004 voltage ds.b 1
12
13 000005 r00 ds.b 1
14 000006 r01 ds.b 1
15 000007 r02 ds.b 1
16 000008 r03 ds.b 1
17 000009 r04 ds.b 1
18 00000A r05 ds.b 1
19
20 segment 'rom'
21 main.l
22 ; initialize SP
23 000000 AE07FF ldw X,#stack_end
24 000003 94 ldw SP,X
25
26 000004 #ifdef 1
27 ; clear RAM0
28 000000 ram0_start.b EQU $0
29 0000FF ram0_end.b EQU $FF
30 000004 AE0000 ldw X,#ram0_start
31 clear_ram0.l
32 000007 7F clr (X)
33 000008 5C incw X
34 000009 A300FF cpw X,#ram0_end
35 00000C R 23F9 jrule clear_ram0
36 00000E #endif
37
38 00000E #ifdef 1
39 ; clear RAM1
40 000100 ram1_start.w EQU $100
41 0005FF ram1_end.w EQU $5FF
42 00000E AE0100 ldw X,#ram1_start
43 clear_ram1.l
44 000011 7F clr (X)
45 000012 5C incw X
46 000013 A305FF cpw X,#ram1_end
47 000016 R 23F9 jrule clear_ram1
STMicroelectronics assembler v4.52 (C)1987-2011 Tue May 31 13:32:51 2011
Page 13 Assembler
f:\stm8\stm8实验\第五次课\复件 (2) ad单次\main.asm
48 000018 #endif
49
50 ; clear stack
51 000600 stack_start.w EQU $600
52 0007FF stack_end.w EQU $7FF
53 000018 AE0600 ldw X,#stack_start
54 clear_stack.l
55 00001B 7F clr (X)
56 00001C 5C incw X
57 00001D A307FF cpw X,#stack_end
58 000020 R 23F9 jrule clear_stack
59
60 000022 intel
61 000022 X 35000000 mov UART2_CR1,#0
62 000026 X 35000000 mov UART2_CR2,#0
63 00002A X 35000000 mov UART2_CR3,#0
64 00002E X 35000000 mov UART2_BRR2,#0
65 000032 X 350D0000 mov UART2_BRR1,#0dh
66 000036 X 350C0000 mov UART2_CR2,#0ch
67
68 00003A X 35000000 mov ADC_CR2,#0 ; A/D结果数据左对齐
69
70 00003E X 5500000000 mov ADC_CR1,0 ; ADC时钟=主时钟/2=1MHZ
71
72 ; ADC转换模式=单次
73
74 ; 禁止ADC转换
75
76 000043 X 35080000 mov ADC_CSR,#8 ; 选择通道8
77
78 000047 X 35010000 mov ADC_TDRH,#1
79
80
81 00004B X 72100000 bset ADC_CR1,#0
82 00004F A664 ld a,#100
83 WAIT_ADC_ON.L
84 000051 4A dec a
85 000052 R 26FD jrne WAIT_ADC_ON ;
;延时一段时间，至少7uS，保证ADC⌨️ 快捷键说明
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