📄 main.lsr
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f:\hrl\stm8s实验\stm8s实验 asm源程序\第一次课 更改时钟源\更改cpu时钟\main.asm
407
408 000000 EXTERN TIM4_CR1.w ; TIM4 Control register 1
409
410 000000 EXTERN TIM4_IER.w ; TIM4 Interrupt enable
;register
411
412 000000 EXTERN TIM4_SR.w ; TIM4 Status register
413
414 000000 EXTERN TIM4_EGR.w ; TIM4 Event Generation
;register
415
416 000000 EXTERN TIM4_CNTR.w ; TIM4 Counter
417
418 000000 EXTERN TIM4_PSCR.w ; TIM4 Prescaler register
419
420 000000 EXTERN TIM4_ARR.w ; TIM4 Auto-reload register
421
422 ; 10-Bit A/D Converter (ADC1)
423 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;
424
425 000000 EXTERN ADC_DB0RH.w ; Data Buffer register 0 High
426
427 000000 EXTERN ADC_DB0RL.w ; Data Buffer register 0 Low
428
429 000000 EXTERN ADC_DB1RH.w ; Data Buffer register 1 High
430
431 000000 EXTERN ADC_DB1RL.w ; Data Buffer register 1 Low
432
433 000000 EXTERN ADC_DB2RH.w ; Data Buffer register 2 High
434
435 000000 EXTERN ADC_DB2RL.w ; Data Buffer register 2 Low
436
437 000000 EXTERN ADC_DB3RH.w ; Data Buffer register 3 High
438
439 000000 EXTERN ADC_DB3RL.w ; Data Buffer register 3 Low
440
441 000000 EXTERN ADC_DB4RH.w ; Data Buffer register 4 High
442
443 000000 EXTERN ADC_DB4RL.w ; Data Buffer register 4 Low
444
445 000000 EXTERN ADC_DB5RH.w ; Data Buffer register 5 High
446
447 000000 EXTERN ADC_DB5RL.w ; Data Buffer register 5 Low
448
449 000000 EXTERN ADC_DB6RH.w ; Data Buffer register 6 High
450
451 000000 EXTERN ADC_DB6RL.w ; Data Buffer register 6 Low
452
453 000000 EXTERN ADC_DB7RH.w ; Data Buffer register 7 High
454
455 000000 EXTERN ADC_DB7RL.w ; Data Buffer register 7 Low
456
457 000000 EXTERN ADC_DB8RH.w ; Data Buffer register 8 High
458
459 000000 EXTERN ADC_DB8RL.w ; Data Buffer register 8 Low
460
STMicroelectronics assembler v4.52 (C)1987-2013 Thu Mar 21 14:39:23 2013
Page 11 Assembler
f:\hrl\stm8s实验\stm8s实验 asm源程序\第一次课 更改时钟源\更改cpu时钟\main.asm
461 000000 EXTERN ADC_DB9RH.w ; Data Buffer register 9 High
462
463 000000 EXTERN ADC_DB9RL.w ; Data Buffer register 9 Low
464
465 000000 EXTERN ADC_CSR.w ; ADC Control/Status Register
466
467 000000 EXTERN ADC_CR1.w ; ADC Configuration Register 1
468
469 000000 EXTERN ADC_CR2.w ; ADC Configuration Register 2
470
471 000000 EXTERN ADC_CR3.w ; ADC Configuration Register 3
472
473 000000 EXTERN ADC_DRH.w ; Data bits High
474
475 000000 EXTERN ADC_DRL.w ; Data bits Low
476
477 000000 EXTERN ADC_TDRH.w ; Schmitt trigger disable High
478
479 000000 EXTERN ADC_TDRL.w ; Schmitt trigger disable Low
480
481 000000 EXTERN ADC_HTRH.w ; High Threshold Register High
482
483 000000 EXTERN ADC_HTRL.w ; High Threshold Register Low
484
485 000000 EXTERN ADC_LTRH.w ; Low Threshold Register High
486
487 000000 EXTERN ADC_LTRL.w ; Low Threshold Register Low
488
489 000000 EXTERN ADC_AWSRH.w ; Analog Watchdog Status
;register High
490
491 000000 EXTERN ADC_AWSRL.w ; Analog Watchdog Status
;register Low
492
493 000000 EXTERN ADC_AWCRH.w ; Analog Watchdog Control
;register High
494
495 000000 EXTERN ADC_AWCRL.w ; Analog Watchdog Control
;register Low
496
497 ; Global configuration register (CFG)
498 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;
499
500 000000 EXTERN CFG_GCR.w ; CFG Global configuration
;register
501
502 ; Interrupt Software Priority Register (ITC)
503 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;;;;;
504
505 000000 EXTERN ITC_SPR1.w ; Interrupt Software priority
;register 1
506
507 000000 EXTERN ITC_SPR2.w ; Interrupt Software priority
;register 2
508
STMicroelectronics assembler v4.52 (C)1987-2013 Thu Mar 21 14:39:23 2013
Page 12 Assembler
f:\hrl\stm8s实验\stm8s实验 asm源程序\第一次课 更改时钟源\更改cpu时钟\main.asm
509 000000 EXTERN ITC_SPR3.w ; Interrupt Software priority
;register 3
510
511 000000 EXTERN ITC_SPR4.w ; Interrupt Software priority
;register 4
512
513 000000 EXTERN ITC_SPR5.w ; Interrupt Software priority
;register 5
514
515 000000 EXTERN ITC_SPR6.w ; Interrupt Software priority
;register 6
516
517 000000 EXTERN ITC_SPR7.w ; Interrupt Software priority
;register 7
518
519 000000 #endif ; __STM8S105C_S__
<END_OF_INCLUSION>
5 segment 'rom'
6 main.l
7 ; initialize SP
8 000000 AE07FF ldw X,#stack_end
9 000003 94 ldw SP,X
10
11 000004 #ifdef 1
12 ; clear RAM0
13 000000 ram0_start.b EQU $0
14 0000FF ram0_end.b EQU $FF
15 000004 AE0000 ldw X,#ram0_start
16 clear_ram0.l
17 000007 7F clr (X)
18 000008 5C incw X
19 000009 A300FF cpw X,#ram0_end
20 00000C R 23F9 jrule clear_ram0
21 00000E #endif
22
23 00000E #ifdef 1
24 ; clear RAM1
25 000100 ram1_start.w EQU $100
26 0005FF ram1_end.w EQU $5FF
27 00000E AE0100 ldw X,#ram1_start
28 clear_ram1.l
29 000011 7F clr (X)
30 000012 5C incw X
31 000013 A305FF cpw X,#ram1_end
32 000016 R 23F9 jrule clear_ram1
33 000018 #endif
34
35 ; clear stack
36 000600 stack_start.w EQU $600
37 0007FF stack_end.w EQU $7FF
38 000018 AE0600 ldw X,#stack_start
39 clear_stack.l
40 00001B 7F clr (X)
41 00001C 5C incw X
42 00001D A307FF cpw X,#stack_end
43 000020 R 23F9 jrule clear_stack
44
45 000022 intel ;intel格式的数值输入方式,不能顶⌨️ 快捷键说明
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