📄 videocap.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
---------------------------------------------------------
--1从SAA7111解码的视频流数据中捕获一桢512*512的图像并存入SRAM中
--2从SRAM中读数据送THS8134用于VGA扫描显示 -----------------------
---系统总状态机以RST0为时钟，从上电的idle态开始循环
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity videocap is
port
(
reset: in std_logic;
clk: in std_logic;
---Key1: in std_logic;
LLC: in std_logic;
--从视频AD中解码的16位RGB数据 其像素时钟为LLC2,13.5MHZ
---RST0: in std_logic;
FLASH_CE,SRAM_CE,SDRAM_CE,USB_CS :out std_logic := '1' ;
--datatest: out std_logic_vector(15 downto 0);
HREF: in std_logic;
VREF:in std_logic;
--WREFtest: out std_logic;
--VIEW: out std_logic_vector(2 downto 0);
sram_addr : out std_logic_vector(17 downto 0);--SRAM 地址线
saa_data_out: in std_logic_vector(15 downto 0); --SAA7111数据
sram_data: inout std_logic_vector(15 downto 0);--SRAM数据线
--datavideo: out std_logic_vector(3 downto 0);--显示数据线
-----------I2C ----------------------------------------------
key2: in std_logic;
--key3: in std_logic;
R :out std_logic_vector( 7 downto 0);
G :out std_logic_vector( 7 downto 0);
B :out std_logic_vector( 7 downto 0);
clkvideo : out std_logic;
sram_n_CE : out std_logic := '1';
sram_n_OE : out std_logic := '1';
sram_n_LB : out std_logic := '1';
sram_n_UB : out std_logic := '1';
sram_n_we : out std_logic := '1';
hs :out std_logic ;
vs :out std_logic ;
--md :in std_logic;
--------------------saa7111----------------------------------
scl : buffer std_logic ;
sda : inout std_logic ;
--- saa_rst : out std_logic ; --reset saa7111
------------------------------------------------------
--key1 : in std_logic ; --WRITE DATA TO SRAM CONTROL
--ths8134 control pins
--说明：ths8134还是需要配置，所以这里还必须把ths8134的控制逻辑加上去，
--而不仅仅是把是使用上面的hs和vs控制就可以了的
ths_sync : out std_logic;
ths_sync_t : out std_logic;
ths_blank : out std_logic;
ths_m1 : out std_logic := '0';
ths_m2 : out std_logic := '0'
);
end videocap;
architecture arch of videocap is
signal out_hs : std_logic ;
signal out_vs : std_logic;
signal dhsync : std_logic ;
signal dvsync : std_logic;
signal out_r ,out_g ,out_b :std_logic_vector( 7 downto 0 );
signal datatemp: std_logic_vector( 7 downto 0 );
constant dhsync_start : integer := 0 ; -- 0
constant dhsync_end : integer := 800; --800
constant dhs_start : integer := 115; --115
constant dhs_end : integer := 755; --755
constant dvsync_start : integer := 1 ; --0
constant dvs_start : integer := 12 ; --32
constant dvs_end : integer := 512; --512
constant dvsync_end : integer := 525 ; --525
signal pixel : std_logic;
signal dths_sync : std_logic;
signal clk4_2 : std_logic;
signal mmd :std_logic;
signal i_dhscnt :std_logic_vector(9 downto 0);
signal i_dvscnt :std_logic_vector(9 downto 0);
signal sram_data_w:std_logic_vector(15 downto 0);
signal sram_data_r:std_logic_vector(15 downto 0);
---------sram control---------------------------
signal W_CE: std_logic;--写状态片选
signal W_WE: std_logic;--写状态写使能
signal W_OE: std_logic;--写状态读使能
signal R_CE: std_logic;--写状态片选
signal R_WE: std_logic;--写状态写使能
signal R_OE: std_logic;--写状态读使能
--------------------------------------------------
component pll
port( inclk0 : IN STD_LOGIC := '0';
---pllena : IN STD_LOGIC := '1';
c0 : OUT STD_LOGIC
);
end component;
signal clkpll: std_logic;
signal w_sram_ce : std_logic ;
signal w_sram_oe : std_logic ;
signal w_sram_we : std_logic ;
signal r_sram_ce : std_logic ;
signal r_sram_oe: std_logic ;
signal r_sram_we : std_logic ;
signal w_addrtemp: std_logic_vector( 17 downto 0);
signal r_addrtemp: std_logic_vector( 17 downto 0);
signal i_r_addrtemp: std_logic_vector( 17 downto 0);
signal i_sram_lb : std_logic ;
signal i_sram_ub : std_logic ;
signal count: std_logic_vector( 1 downto 0);
signal addref: std_logic;
-------------------i2c-----------------------------------
begin
a1:pll
port map(inclk0=>LLC, c0=>clkpll);
--a1:fifor
--port map( clock=>key3, data=>sram_data_rin,q=>sram_data_rout);
--a2:fifow
--port map( clock=>w_sram_we, data=>sram_data_win,q=>sram_data_wo
ths_m1<= '0';
ths_m2<= '0';
sram_n_LB <= '0';
sram_n_UB <= '0';
process(mmd)
begin
case mmd is
when '0' =>
sram_n_CE <=W_CE ;
sram_n_OE <= W_OE ;
sram_n_we <= W_WE ;
sram_addr<= w_addrtemp;
--sram_data<= sram_data_w;
when '1' =>
r_sram_ce<='0';
r_sram_we<='1';
sram_n_CE <=R_CE;
sram_n_OE <= R_OE;
sram_n_we <= R_WE ;
sram_addr<= r_addrtemp;
when others =>
sram_n_CE <='1';
sram_n_OE <='1';
sram_n_we <='1';
end case;
end process;
--------mode select ------------------------------------------------
process(mmd )
begin
if mmd ='1' then
R_CE<='0';
R_WE<='1';
R_OE<='0';
else
R_CE<='1';
R_WE<='1';
R_OE<='1';
end if;
end process;
--------------------------------------------------------------
---------------------------------------------------------
-- generate dhs signal
---------------------------------------------------------
process (clk ,reset)
begin
if (reset='0') then
i_dhscnt <= "0000000000";
dhsync <= '0';
out_hs <= '0';
elsif (clk'event and clk='1') then
i_dhscnt <= i_dhscnt + 1;
if (i_dhscnt = 1) then --dhsync_start = 1
dhsync <= '1';
elsif (i_dhscnt= 115 ) then
out_hs <= '1'; --dhs_start = 115
elsif (i_dhscnt = 755 ) then --dhs_end = 755
out_hs <= '0';
elsif (i_dhscnt= 780 ) then --dhsync_end = 800
i_dhscnt <= "0000000000";
dhsync <= '0';
end if;
end if;
end process;
--------------------------------------------------------
-- generate dvs signal
--------------------------------------------------------
process (dhsync,reset)
begin
if (reset='0') then
i_dvscnt <= "0000000000" ;
dvsync <= '0';
out_vs <= '0';
elsif (dhsync'event and dhsync='1') then
i_dvscnt <= i_dvscnt + 1;
if (i_dvscnt=dvsync_start) then --dvsync_start = 1
dvsync<='1';
elsif (i_dvscnt=dvs_start) then --dvs_start = 3
out_vs <= '1';
elsif (i_dvscnt=dvs_end) then -- dvs_end = 512
out_vs <= '0';
elsif (i_dvscnt= dvsync_end) then --dvsync_end = 525
i_dvscnt <= "0000000000" ;
dvsync <='0';
end if;
end if;
end process;
----------------数据递增-----------------------------
process(VREF)
variable count : integer range 0 to 100;
begin
if( VREF'event and VREF = '1') then --key down
count:= count+1 ;
end if;
if count=20 then
mmd<='0';
else
mmd<='1';
end if;
end process;
------------------写数据到缓存-----------------------
process(clkpll,HREF,VREF)
---variable count: integer range 0 to 3;
begin
if mmd = '0' then
if clkpll'event and clkpll='1' then
if HREF='1' and VREF='1' then
count<=count+1;
else
count<="ZZ";
end if;
end if;
else
count<="ZZ";
end if;
end process;
process(count)
begin
case count is
when "00" =>
W_WE<='1';
if HREF='1' then
w_addrtemp<=w_addrtemp+"000000000000000001";
else
w_addrtemp<="000000000000000000";
end if;
sram_data<="ZZZZZZZZZZZZZZZZ";
--w_sram_we<='1';
--sram_data_w<=sram_data_w+"0000000000000001";
----sram_data<=sram_data_w;
when "01" =>
W_WE<='1';
when "10" =>
W_WE<='0';
sram_data<=saa_data_out;
when "11"=>
W_WE<='1';
when others =>
W_WE<='1';
end case;
end process;
process( mmd ,HREF)
begin
if mmd = '0' then
if HREF='1' and VREF='1' then
W_CE<='0' ;
else
W_CE<='1' ;
end if;
else
W_CE<='1' ;
end if;
end process;
----------------------------------------------------------------
process(mmd,i_dhscnt)
begin
if mmd='1' then
if out_vs <= '1' then
if i_dhscnt>=35 and i_dhscnt<=754 then
addref<='1' ;
else
addref<='0' ;
end if;
else
addref<='0';
end if;
else
addref<='0';
end if ;
end process;
------------------读数据送显示器---------------------
process(clk,mmd,i_dhscnt)
begin
if mmd='1' then
if clk'event and clk='0' then
if addref<='1' then
if r_addrtemp="101100111111111111" then
r_addrtemp<="000000000000000000";
else
r_addrtemp<=r_addrtemp+"000000000000000001";
end if;
end if ;
end if ;
else
r_addrtemp<="000000000000000000";
end if;
end process;
process(clk,mmd)
begin
if mmd='1' then
if clk'event and clk='1' then
if pixel<='1' and out_vs <= '1' then
out_r<= sram_data( 15 downto 11) & "111"; --sram_data( 7 downto 0)
out_g<= sram_data( 10 downto 5 ) & "11"; --sram_data( 7 downto 0);
out_b<= sram_data( 4 downto 0 ) & "111" ;
end if;
end if;
else
sram_data_r<="ZZZZZZZZZZZZZZZZ";
end if;
end process;
--------------------------------------------------
clkvideo<=clk;
process(i_dhscnt)
begin
if i_dhscnt>=120 and i_dhscnt<=631 then
pixel<='1' ;
else
pixel<='0' ;
end if;
end process;
--output
process(clk)
begin
if mmd='1' then
if( clk'event and clk= '1') then
if (pixel='1' and out_vs <= '1') then
R <= out_r; --sram_data( 7 downto 0)
G <= out_g; --sram_data( 7 downto 0);
B <= out_b; --sram_data( 7 downto 0);
--G <= sram_data_r( 10 downto 5 ) & "11"; --sram_data( 7 downto 0);
---B <= sram_data_r( 4 downto 0 ) & "111" ; --sram_data( 7 downto 0);
else
R <= "00000000" ;
G <= "00000000" ;
B <= "00000000" ;
end if ;
end if;
else
R <= "00000000" ;
G <= "00000000" ;
B <= "00000000" ;
end if;
end process;
hs <= out_hs ;
vs <= out_vs ;
ths_sync <= dths_sync ;
dths_sync <= out_hs ; -- syn
ths_blank <= out_vs ;
--------------------------i2c------------------------------------------------------------
end arch;
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