📄 e100_557.h
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//-------------------------------------------------------------------------
// NOP Command Block (NOP_CB)
//-------------------------------------------------------------------------
typedef struct _NOP_CB_STRUC {
CB_HEADER_STRUC NopCBHeader;
} NOP_CB_STRUC, *PNOP_CB_STRUC;
//-------------------------------------------------------------------------
// Individual Address Command Block (IA_CB)
//-------------------------------------------------------------------------
typedef struct _IA_CB_STRUC {
CB_HEADER_STRUC IaCBHeader;
UCHAR IaAddress[ETHERNET_ADDRESS_LENGTH];
} IA_CB_STRUC, *PIA_CB_STRUC;
//-------------------------------------------------------------------------
// Configure Command Block (CONFIG_CB)
//-------------------------------------------------------------------------
typedef struct _CONFIG_CB_STRUC {
CB_HEADER_STRUC ConfigCBHeader;
UCHAR ConfigBytes[CB_CFIG_BYTE_COUNT];
} CONFIG_CB_STRUC, *PCONFIG_CB_STRUC;
//-------------------------------------------------------------------------
// MultiCast Command Block (MULTICAST_CB)
//-------------------------------------------------------------------------
typedef struct _MULTICAST_CB_STRUC {
CB_HEADER_STRUC McCBHeader;
USHORT McCount; // Number of multicast addresses
UCHAR McAddress[(ETHERNET_ADDRESS_LENGTH * MAX_MULTICAST_ADDRESSES)];
} MULTICAST_CB_STRUC, *PMULTICAST_CB_STRUC;
//-------------------------------------------------------------------------
// WakeUp Filter Command Block (FILTER_CB)
//-------------------------------------------------------------------------
typedef struct _FILTER_CB_STRUC {
CB_HEADER_STRUC FilterCBHeader;
ULONG Pattern[16];
}FILTER_CB_STRUC , *PFILTER_CB_STRUC ;
//-------------------------------------------------------------------------
// Dump Command Block (DUMP_CB)
//-------------------------------------------------------------------------
typedef struct _DUMP_CB_STRUC {
CB_HEADER_STRUC DumpCBHeader;
ULONG DumpAreaAddress; // Dump Buffer Area Address
} DUMP_CB_STRUC, *PDUMP_CB_STRUC;
//-------------------------------------------------------------------------
// Dump Area structure definition
//-------------------------------------------------------------------------
typedef struct _DUMP_AREA_STRUC {
UCHAR DumpBuffer[DUMP_BUFFER_SIZE];
} DUMP_AREA_STRUC, *PDUMP_AREA_STRUC;
//-------------------------------------------------------------------------
// Diagnose Command Block (DIAGNOSE_CB)
//-------------------------------------------------------------------------
typedef struct _DIAGNOSE_CB_STRUC {
CB_HEADER_STRUC DiagCBHeader;
} DIAGNOSE_CB_STRUC, *PDIAGNOSE_CB_STRUC;
//-------------------------------------------------------------------------
// Transmit Command Block (TxCB)
//-------------------------------------------------------------------------
typedef struct _GENERIC_TxCB {
CB_HEADER_STRUC TxCbHeader;
ULONG TxCbTbdPointer; // TBD address
USHORT TxCbCount; // Data Bytes In TCB past header
UCHAR TxCbThreshold; // TX Threshold for FIFO Extender
UCHAR TxCbTbdNumber;
ETH_TX_BUFFER_STRUC TxCbData;
ULONG pad0;
ULONG pad1;
ULONG pad2;
ULONG pad3;
} TXCB_STRUC, *PTXCB_STRUC;
//-------------------------------------------------------------------------
// Transmit Buffer Descriptor (TBD)
//-------------------------------------------------------------------------
typedef struct _TBD_STRUC {
ULONG TbdBufferAddress; // Physical Transmit Buffer Address
unsigned TbdCount :14;
unsigned :1 ; // always 0
unsigned EndOfList:1 ; // EL bit in Tbd
unsigned :16; // field that is always 0's in a TBD
} TBD_STRUC, *PTBD_STRUC;
//-------------------------------------------------------------------------
// Receive Frame Descriptor (RFD)
//-------------------------------------------------------------------------
typedef struct _RFD_STRUC {
CB_HEADER_STRUC RfdCbHeader;
ULONG RfdRbdPointer; // Receive Buffer Descriptor Addr
USHORT RfdActualCount; // Number Of Bytes Received
USHORT RfdSize; // Number Of Bytes In RFD
ETH_RX_BUFFER_STRUC RfdBuffer; // Data buffer in RFD
} RFD_STRUC, *PRFD_STRUC;
//-------------------------------------------------------------------------
// Receive Buffer Descriptor (RBD)
//-------------------------------------------------------------------------
typedef struct _RBD_STRUC {
USHORT RbdActualCount; // Number Of Bytes Received
USHORT RbdFiller;
ULONG RbdLinkAddress; // Link To Next RBD
ULONG RbdRcbAddress; // Receive Buffer Address
USHORT RbdSize; // Receive Buffer Size
USHORT RbdFiller1;
} RBD_STRUC, *PRBD_STRUC;
#pragma pack()
//-------------------------------------------------------------------------
// 82557 PCI Register Definitions
// Refer To The PCI Specification For Detailed Explanations
//-------------------------------------------------------------------------
//- Register Offsets
#define PCI_VENDOR_ID_REGISTER 0x00 // PCI Vendor ID Register
#define PCI_DEVICE_ID_REGISTER 0x02 // PCI Device ID Register
#define PCI_CONFIG_ID_REGISTER 0x00 // PCI Configuration ID Register
#define PCI_COMMAND_REGISTER 0x04 // PCI Command Register
#define PCI_STATUS_REGISTER 0x06 // PCI Status Register
#define PCI_REV_ID_REGISTER 0x08 // PCI Revision ID Register
#define PCI_CLASS_CODE_REGISTER 0x09 // PCI Class Code Register
#define PCI_CACHE_LINE_REGISTER 0x0C // PCI Cache Line Register
#define PCI_LATENCY_TIMER 0x0D // PCI Latency Timer Register
#define PCI_HEADER_TYPE 0x0E // PCI Header Type Register
#define PCI_BIST_REGISTER 0x0F // PCI Built-In SelfTest Register
#define PCI_BAR_0_REGISTER 0x10 // PCI Base Address Register 0
#define PCI_BAR_1_REGISTER 0x14 // PCI Base Address Register 1
#define PCI_BAR_2_REGISTER 0x18 // PCI Base Address Register 2
#define PCI_BAR_3_REGISTER 0x1C // PCI Base Address Register 3
#define PCI_BAR_4_REGISTER 0x20 // PCI Base Address Register 4
#define PCI_BAR_5_REGISTER 0x24 // PCI Base Address Register 5
#define PCI_SUBVENDOR_ID_REGISTER 0x2C // PCI SubVendor ID Register
#define PCI_SUBDEVICE_ID_REGISTER 0x2E // PCI SubDevice ID Register
#define PCI_EXPANSION_ROM 0x30 // PCI Expansion ROM Base Register
#define PCI_INTERRUPT_LINE 0x3C // PCI Interrupt Line Register
#define PCI_INTERRUPT_PIN 0x3D // PCI Interrupt Pin Register
#define PCI_MIN_GNT_REGISTER 0x3E // PCI Min-Gnt Register
#define PCI_MAX_LAT_REGISTER 0x3F // PCI Max_Lat Register
#define PCI_NODE_ADDR_REGISTER 0x40 // PCI Node Address Register
//-------------------------------------------------------------------------
// PHY 100 MDI Register/Bit Definitions
//-------------------------------------------------------------------------
// MDI register set
#define MDI_CONTROL_REG 0x00 // MDI control register
#define MDI_STATUS_REG 0x01 // MDI Status regiser
#define PHY_ID_REG_1 0x02 // Phy indentification reg (word 1)
#define PHY_ID_REG_2 0x03 // Phy indentification reg (word 2)
#define AUTO_NEG_ADVERTISE_REG 0x04 // Auto-negotiation advertisement
#define AUTO_NEG_LINK_PARTNER_REG 0x05 // Auto-negotiation link partner ability
#define AUTO_NEG_EXPANSION_REG 0x06 // Auto-negotiation expansion
#define AUTO_NEG_NEXT_PAGE_REG 0x07 // Auto-negotiation next page transmit
#define EXTENDED_REG_0 0x10 // Extended reg 0 (Phy 100 modes)
#define EXTENDED_REG_1 0x14 // Extended reg 1 (Phy 100 error indications)
#define NSC_CONG_CONTROL_REG 0x17 // National (TX) congestion control
#define NSC_SPEED_IND_REG 0x19 // National (TX) speed indication
#define PHY_EQUALIZER_REG 0x1A // Register for the Phy Equalizer values
// MDI Control register bit definitions
#define MDI_CR_COLL_TEST_ENABLE BIT_7 // Collision test enable
#define MDI_CR_FULL_HALF BIT_8 // FDX =1, half duplex =0
#define MDI_CR_RESTART_AUTO_NEG BIT_9 // Restart auto negotiation
#define MDI_CR_ISOLATE BIT_10 // Isolate PHY from MII
#define MDI_CR_POWER_DOWN BIT_11 // Power down
#define MDI_CR_AUTO_SELECT BIT_12 // Auto speed select enable
#define MDI_CR_10_100 BIT_13 // 0 = 10Mbs, 1 = 100Mbs
#define MDI_CR_LOOPBACK BIT_14 // 0 = normal, 1 = loopback
#define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset
// MDI Status register bit definitions
#define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities
#define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected
#define MDI_SR_LINK_STATUS BIT_2 // Link Status -- 1 = link
#define MDI_SR_AUTO_SELECT_CAPABLE BIT_3 // Auto speed select capable
#define MDI_SR_REMOTE_FAULT_DETECT BIT_4 // Remote fault detect
#define MDI_SR_AUTO_NEG_COMPLETE BIT_5 // Auto negotiation complete
#define MDI_SR_10T_HALF_DPX BIT_11 // 10BaseT Half Duplex capable
#define MDI_SR_10T_FULL_DPX BIT_12 // 10BaseT full duplex capable
#define MDI_SR_TX_HALF_DPX BIT_13 // TX Half Duplex capable
#define MDI_SR_TX_FULL_DPX BIT_14 // TX full duplex capable
#define MDI_SR_T4_CAPABLE BIT_15 // T4 capable
// Auto-Negotiation advertisement register bit definitions
#define NWAY_AD_SELCTOR_FIELD BIT_0_4 // identifies supported protocol
#define NWAY_AD_ABILITY BIT_5_12 // technologies that are supported
#define NWAY_AD_10T_HALF_DPX BIT_5 // 10BaseT Half Duplex capable
#define NWAY_AD_10T_FULL_DPX BIT_6 // 10BaseT full duplex capable
#define NWAY_AD_TX_HALF_DPX BIT_7 // TX Half Duplex capable
#define NWAY_AD_TX_FULL_DPX BIT_8 // TX full duplex capable
#define NWAY_AD_T4_CAPABLE BIT_9 // T4 capable
#define NWAY_AD_REMOTE_FAULT BIT_13 // indicates local remote fault
#define NWAY_AD_RESERVED BIT_14 // reserved
#define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)
// Auto-Negotiation link partner ability register bit definitions
#define NWAY_LP_SELCTOR_FIELD BIT_0_4 // identifies supported protocol
#define NWAY_LP_ABILITY BIT_5_9 // technologies that are supported
#define NWAY_LP_REMOTE_FAULT BIT_13 // indicates partner remote fault
#define NWAY_LP_ACKNOWLEDGE BIT_14 // acknowledge
#define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)
// Auto-Negotiation expansion register bit definitions
#define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY
#define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received
#define NWAY_EX_NEXT_PAGE_ABLE BIT_2 // local is next page able
#define NWAY_EX_LP_NEXT_PAGE_ABLE BIT_3 // partner is next page able
#define NWAY_EX_PARALLEL_DET_FLT BIT_4 // parallel detection fault
#define NWAY_EX_RESERVED BIT_5_15 // reserved
// PHY 100 Extended Register 0 bit definitions
#define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex
#define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs
#define PHY_100_ER0_WAKE_UP BIT_2 // Wake up DAC
#define PHY_100_ER0_RESERVED BIT_3_4 // Reserved
#define PHY_100_ER0_REV_CNTRL BIT_5_7 // Revsion control (A step = 000)
#define PHY_100_ER0_FORCE_FAIL BIT_8 // Force Fail is enabled
#define PHY_100_ER0_TEST BIT_9_13 // Revsion control (A step = 000)
#define PHY_100_ER0_LINKDIS BIT_14 // Link integrity test is disabled
#define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled
// PHY 100 Extended Register 1 bit definitions
#define PHY_100_ER1_RESERVED BIT_0_8 // Reserved
#define PHY_100_ER1_CH2_DET_ERR BIT_9 // Channel 2 EOF detection error
#define PHY_100_ER1_MANCH_CODE_ERR BIT_10 // Manchester code error
#define PHY_100_ER1_EOP_ERR BIT_11 // EOP error
#define PHY_100_ER1_BAD_CODE_ERR BIT_12 // bad code error
#define PHY_100_ER1_INV_CODE_ERR BIT_13 // invalid code error
#define PHY_100_ER1_DC_BAL_ERR BIT_14 // DC balance error
#define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error
// PHY TX Register/Bit definitions
#define PHY_TX_STATUS_CTRL_REG 0x10
#define PHY_TX_POLARITY_MASK BIT_8 // register 10h bit 8 (the polarity bit)
#define PHY_TX_NORMAL_POLARITY 0 // register 10h bit 8 =0 (normal polarity)
#define PHY_TX_SPECIAL_CTRL_REG 0x11
#define AUTO_POLARITY_DISABLE BIT_4 // register 11h bit 4 (0=enable, 1=disable)
#define PHY_TX_REG_18 0x18 // Error counter register
// National Semiconductor TX phy congestion control register bit definitions
#define NSC_TX_CONG_TXREADY BIT_10 // Makes TxReady an input
#define NSC_TX_CONG_ENABLE BIT_8 // Enables congestion control
#define NSC_TX_CONG_F_CONNECT BIT_5 // Enables congestion control
// National Semiconductor TX phy speed indication register bit definitions
#define NSC_TX_SPD_INDC_SPEED BIT_6 // 0 = 100mb, 1=10mb
#endif // _E100_557_H
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