📄 e100_557.h
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// byte 13 bit definitions -- pre-defined all zeros
// byte 14 bit definitions -- pre-defined 0xf2
// byte 15 bit definitions
#define CB_CFIG_PROMISCUOUS BIT_0 // Promiscuous Mode Enable
#define CB_CFIG_BROADCAST_DIS BIT_1 // Broadcast Mode Disable
#define CB_CFIG_CRS_OR_CDT BIT_7 // CRS Or CDT
// byte 16 bit definitions -- pre-defined all zeros
// byte 17 bit definitions -- pre-defined 0x40
// byte 18 bit definitions
#define CB_CFIG_STRIPPING BIT_0 // Stripping Disabled
#define CB_CFIG_PADDING BIT_1 // Padding Disabled
#define CB_CFIG_CRC_IN_MEM BIT_2 // Transfer CRC To Memory
// byte 19 bit definitions
#define CB_CFIG_FORCE_FDX BIT_6 // Force Full Duplex
#define CB_CFIG_FDX_ENABLE BIT_7 // Full Duplex Enabled
// byte 20 bit definitions
#define CB_CFIG_MULTI_IA BIT_6 // Multiple IA Addr
// byte 21 bit definitions
#define CB_CFIG_MULTICAST_ALL BIT_3 // Multicast All
//-------------------------------------------------------------------------
// Receive Frame Descriptor Fields
//-------------------------------------------------------------------------
//- RFD Status Bits
#define RFD_RECEIVE_COLLISION BIT_0 // Collision detected on Receive
#define RFD_IA_MATCH BIT_1 // Indv Address Match Bit
#define RFD_RX_ERR BIT_4 // RX_ERR pin on Phy was set
#define RFD_FRAME_TOO_SHORT BIT_7 // Receive Frame Short
#define RFD_DMA_OVERRUN BIT_8 // Receive DMA Overrun
#define RFD_NO_RESOURCES BIT_9 // No Buffer Space
#define RFD_ALIGNMENT_ERROR BIT_10 // Alignment Error
#define RFD_CRC_ERROR BIT_11 // CRC Error
#define RFD_STATUS_OK BIT_13 // RFD OK Bit
#define RFD_STATUS_COMPLETE BIT_15 // RFD Complete Bit
//- RFD Command Bits
#define RFD_EL_BIT BIT_15 // RFD EL Bit
#define RFD_S_BIT BIT_14 // RFD Suspend Bit
#define RFD_H_BIT BIT_4 // Header RFD Bit
#define RFD_SF_BIT BIT_3 // RFD Flexible Mode
//- RFD misc bits
#define RFD_EOF_BIT BIT_15 // RFD End-Of-Frame Bit
#define RFD_F_BIT BIT_14 // RFD Buffer Fetch Bit
#define RFD_ACT_COUNT_MASK BIT_0_13 // RFD Actual Count Mask
#define RFD_HEADER_SIZE 0x10 // Size of RFD Header (16 bytes)
//-------------------------------------------------------------------------
// Receive Buffer Descriptor Fields
//-------------------------------------------------------------------------
#define RBD_EOF_BIT BIT_15 // RBD End-Of-Frame Bit
#define RBD_F_BIT BIT_14 // RBD Buffer Fetch Bit
#define RBD_ACT_COUNT_MASK BIT_0_13 // RBD Actual Count Mask
#define SIZE_FIELD_MASK BIT_0_13 // Size of the associated buffer
#define RBD_EL_BIT BIT_15 // RBD EL Bit
//-------------------------------------------------------------------------
// Size Of Dump Buffer
//-------------------------------------------------------------------------
#define DUMP_BUFFER_SIZE 600 // size of the dump buffer
//-------------------------------------------------------------------------
// Self Test Results
//-------------------------------------------------------------------------
#define CB_SELFTEST_FAIL_BIT BIT_12
#define CB_SELFTEST_DIAG_BIT BIT_5
#define CB_SELFTEST_REGISTER_BIT BIT_3
#define CB_SELFTEST_ROM_BIT BIT_2
#define CB_SELFTEST_ERROR_MASK ( \
CB_SELFTEST_FAIL_BIT | CB_SELFTEST_DIAG_BIT | \
CB_SELFTEST_REGISTER_BIT | CB_SELFTEST_ROM_BIT)
//-------------------------------------------------------------------------
// Driver Configuration Default Parameters for the 557
// Note: If the driver uses any defaults that are different from the chip's
// defaults, it will be noted below
//-------------------------------------------------------------------------
// Byte 0 (byte count) default
#define CB_557_CFIG_DEFAULT_PARM0 CB_CFIG_BYTE_COUNT
// Byte 1 (fifo limits) default
#define DEFAULT_TX_FIFO_LIMIT 0x08
#define DEFAULT_RX_FIFO_LIMIT 0x08
#define CB_557_CFIG_DEFAULT_PARM1 0x88
// Byte 2 (IFS) default
#define CB_557_CFIG_DEFAULT_PARM2 0x00
// Byte 3 (reserved) default
#define CB_557_CFIG_DEFAULT_PARM3 0x00
// Byte 4 (Rx DMA min count) default
#define CB_557_CFIG_DEFAULT_PARM4 0x00
// Byte 5 (Tx DMA min count, DMA min count enable) default
#define CB_557_CFIG_DEFAULT_PARM5 0x00
// Byte 6 (Late SCB, TNO int, CI int, Save bad frames) default
#define CB_557_CFIG_DEFAULT_PARM6 0x32
// Byte 7 (Discard short frames, underrun retry) default
// note: disc short frames will be enabled
#define DEFAULT_UNDERRUN_RETRY 0x01
#define CB_557_CFIG_DEFAULT_PARM7 0x01
// Byte 8 (MII or 503) default
// note: MII will be the default
#define CB_557_CFIG_DEFAULT_PARM8 0x01
// Byte 9 - Power management for 82558B, 82559
#define CB_WAKE_ON_LINK_BYTE9 0x20
#define CB_WAKE_ON_ARP_PKT_BYTE9 0x40
#define CB_557_CFIG_DEFAULT_PARM9 0
// Byte 10 (scr addr insertion, preamble, loopback) default
#define CB_557_CFIG_DEFAULT_PARM10 0x2e
// Byte 11 (linear priority) default
#define CB_557_CFIG_DEFAULT_PARM11 0x00
// Byte 12 (IFS,linear priority mode) default
#define CB_557_CFIG_DEFAULT_PARM12 0x60
// Byte 13 (reserved) default
#define CB_557_CFIG_DEFAULT_PARM13 0x00
// Byte 14 (reserved) default
#define CB_557_CFIG_DEFAULT_PARM14 0xf2
// Byte 15 (promiscuous, broadcast, CRS/CDT) default
#define CB_557_CFIG_DEFAULT_PARM15 0xea
// Byte 16 (reserved) default
#define CB_557_CFIG_DEFAULT_PARM16 0x00
// Byte 17 (reserved) default
#define CB_557_CFIG_DEFAULT_PARM17 0x40
// Byte 18 (Stripping, padding, Rcv CRC in mem) default
// note: padding will be enabled
#define CB_557_CFIG_DEFAULT_PARM18 0xf2
// Byte 19 (reserved) default
// note: full duplex is enabled if FDX# pin is 0
#define CB_557_CFIG_DEFAULT_PARM19 0x80
// Byte 20 (multi-IA) default
#define CB_557_CFIG_DEFAULT_PARM20 0x3f
// Byte 21 (multicast all) default
#define CB_557_CFIG_DEFAULT_PARM21 0x05
#pragma pack(1)
//-------------------------------------------------------------------------
// Ethernet Frame Structure
//-------------------------------------------------------------------------
//- Ethernet 6-byte Address
typedef struct _ETH_ADDRESS_STRUC {
UCHAR EthNodeAddress[ETHERNET_ADDRESS_LENGTH];
} ETH_ADDRESS_STRUC, *PETH_ADDRESS_STRUC;
//- Ethernet 14-byte Header
typedef struct _ETH_HEADER_STRUC {
UCHAR Destination[ETHERNET_ADDRESS_LENGTH];
UCHAR Source[ETHERNET_ADDRESS_LENGTH];
USHORT TypeLength;
} ETH_HEADER_STRUC, *PETH_HEADER_STRUC;
//- Ethernet Buffer (Including Ethernet Header) for Transmits
typedef struct _ETH_TX_BUFFER_STRUC {
ETH_HEADER_STRUC TxMacHeader;
UCHAR TxBufferData[(TCB_BUFFER_SIZE - sizeof(ETH_HEADER_STRUC))];
} ETH_TX_BUFFER_STRUC, *PETH_TX_BUFFER_STRUC;
typedef struct _ETH_RX_BUFFER_STRUC {
ETH_HEADER_STRUC RxMacHeader;
UCHAR RxBufferData[(RCB_BUFFER_SIZE - sizeof(ETH_HEADER_STRUC))];
} ETH_RX_BUFFER_STRUC, *PETH_RX_BUFFER_STRUC;
//-------------------------------------------------------------------------
// 82557 Data Structures
//-------------------------------------------------------------------------
//-------------------------------------------------------------------------
// Self test
//-------------------------------------------------------------------------
typedef struct _SELF_TEST_STRUC {
ULONG StSignature; // Self Test Signature
ULONG StResults; // Self Test Results
} SELF_TEST_STRUC, *PSELF_TEST_STRUC;
//-------------------------------------------------------------------------
// Control/Status Registers (CSR)
//-------------------------------------------------------------------------
typedef struct _CSR_STRUC {
USHORT ScbStatus; // SCB Status register
UCHAR ScbCommandLow; // SCB Command register (low byte)
UCHAR ScbCommandHigh; // SCB Command register (high byte)
ULONG ScbGeneralPointer; // SCB General pointer
ULONG Port; // PORT register
USHORT FlashControl; // Flash Control register
USHORT EepromControl; // EEPROM control register
ULONG MDIControl; // MDI Control Register
ULONG RxDMAByteCount; // Receive DMA Byte count register
} CSR_STRUC, *PCSR_STRUC;
//-------------------------------------------------------------------------
// Error Counters
//-------------------------------------------------------------------------
typedef struct _ERR_COUNT_STRUC {
ULONG XmtGoodFrames; // Good frames transmitted
ULONG XmtMaxCollisions; // Fatal frames -- had max collisions
ULONG XmtLateCollisions; // Fatal frames -- had a late coll.
ULONG XmtUnderruns; // Transmit underruns (fatal or re-transmit)
ULONG XmtLostCRS; // Frames transmitted without CRS
ULONG XmtDeferred; // Deferred transmits
ULONG XmtSingleCollision; // Transmits that had 1 and only 1 coll.
ULONG XmtMultCollisions; // Transmits that had multiple coll.
ULONG XmtTotalCollisions; // Transmits that had 1+ collisions.
ULONG RcvGoodFrames; // Good frames received
ULONG RcvCrcErrors; // Aligned frames that had a CRC error
ULONG RcvAlignmentErrors; // Receives that had alignment errors
ULONG RcvResourceErrors; // Good frame dropped due to lack of resources
ULONG RcvOverrunErrors; // Overrun errors - bus was busy
ULONG RcvCdtErrors; // Received frames that encountered coll.
ULONG RcvShortFrames; // Received frames that were to short
ULONG CommandComplete; // A005h indicates cmd completion
} ERR_COUNT_STRUC, *PERR_COUNT_STRUC;
//-------------------------------------------------------------------------
// Command Block (CB) Generic Header Structure
//-------------------------------------------------------------------------
typedef struct _CB_HEADER_STRUC {
USHORT CbStatus; // Command Block Status
USHORT CbCommand; // Command Block Command
ULONG CbLinkPointer; // Link To Next CB
} CB_HEADER_STRUC, *PCB_HEADER_STRUC;
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