8139.h

rtl8139网卡在Windows2000/xp下的驱动程序源代码,无线网卡驱动

enum RTL8139_registers {
	MAC0 = 0,		      // Ethernet hardware address  IDR0
	MAR0 = 8,		      // Multicast 多点传送 Register 0
	TxStatus0 = 0x10,	  // Transmit status of descriptor 0 (Four 32bit registers)
	TxAddr0 = 0x20,		  // Transmit Start Address of descriptor 0 (Four 32bit registers)
	RxBuf = 0x30,         // Receive Buffer Start Address
	RxEarlyCnt = 0x34,    // Early Receive Byte Count Register  R
	RxEarlyStatus = 0x36, // Early Receive Status Register  R
	ChipCmd = 0x37,       // Command Register
	RxBufPtr = 0x38,      // Current Address of Packet Read  当前读到的包地址
	RxBufAddr = 0x3A,     // Current Buffer Address 初值为0x0000，它反映了接收缓冲区中接收到的字节总数
	IntrMask = 0x3C,      // Interrupt Mask Register
	IntrStatus = 0x3E,    // Interrupt Status Register
	TxConfig = 0x40,      // Transmit Configuration Register
	RxConfig = 0x44,      // Receive Configuration Register
	Timer = 0x48,		  // Timer Count Register 32位通用定时器，写入任何值都会复位定时器并开始从0计数
	RxMissed = 0x4C,	  // Missed Packet Counter 表示因Rx FIFO溢出而丢弃的包数量
	Cmd93C46 = 0x50,      // 93C46 Command Register
	Config0 = 0x51,       // Configuration Register 0
	Config1 = 0x52,       // Configuration Register 1
	TimIntReg = 0x54,     // Timer Interrupt Register
	MediaStatus = 0x58,   // Media Status Register
	Config3 = 0x59,       // Configuration Register 3
	Config4 = 0x5A,		  // Configuration Register 4
	MultiIntr = 0x5C,     // Multiple Interrupt Select
	TxStatusAll = 0x60,   // Transmit Status of All Descriptors
	BasicModeCtrl = 0x62, // Basic Mode Control Register
	BasicModeStatus =0x64,// Basic Mode Status Register
	NWayAdvert = 0x66,    // Auto-Negotiation Advertisement Register
	NWayLPAR = 0x68,      // Auto-Negotiation Link Partner Register
	NWayExpansion = 0x6A, // Auto-Negotiation Expansion Register
	CSCR = 0x74,		  // CS Configuration Register
	Config5 = 0xD8,		  // Configuration Register 5
};

enum ClearBitMasks {
	MultiIntrClear = 0xF000,
	ChipCmdClear = 0xE2,
	Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
};

enum ChipCmdBits {
	CmdReset = 0x10,
	CmdRxEnb = 0x08,
	CmdTxEnb = 0x04,
	RxBufEmpty = 0x01,  //接收缓冲区空，没有包存储在接收环状缓冲区中
};

/* Interrupt register bits */
enum IntrStatusBits {
	PCIErr = 0x8000,
	PCSTimeout = 0x4000,
	RxFIFOOver = 0x40, //接收FIFO溢出
	RxUnderrun = 0x20,
	RxOverflow = 0x10, //接收环状缓冲区资源耗尽了
	TxErr = 0x08,    //表明包传送由于过量的冲突而丢弃（根据TXRR的设置）
	TxOK = 0x04,     // 表明包传送成功结束
	RxErr = 0x02,    // 接收包有CRC错误或帧对齐错误
	RxOK = 0x01,     // 表明包接收成功结束
};
enum TxStatusBits {
	TxHostOwns = 0x2000,
	TxUnderrun = 0x4000,  // 为1则表明在包传送期间，传送FIFO耗尽了
	TxStatOK = 0x8000,    // 为1则表明包传送成功结束，传送不再发生
	TxOutOfWindow = 0x20000000,
	TxAborted = 0x40000000,  // 为1则表明包传送被丢弃了
	TxCarrierLost = 0x80000000,
};
enum RxStatusBits {
	RxMulticast = 0x8000,
	RxPhysical = 0x4000,
	RxBroadcast = 0x2000,
	RxBadSymbol = 0x0020,
	RxRunt = 0x0010,
	RxTooLong = 0x0008,
	RxCRCErr = 0x0004,
	RxBadAlign = 0x0002,
	RxStatusOK = 0x0001,
};

/* Bits in RxConfig. */
enum rx_mode_bits {
	AcceptErr = 0x20,
	AcceptRunt = 0x10,
	AcceptBroadcast = 0x08,//Accept Broadcast packets:
	AcceptMulticast = 0x04,//Accept Multicast packets:
	AcceptMyPhys = 0x02,  //Accept Physical Match packets:
	AcceptAllPhys = 0x01,
};

/* Bits in TxConfig. */
enum tx_config_bits {
	TxIFG1 = (1 << 25),	/* Interframe Gap Time */
	TxIFG0 = (1 << 24),	/* Enabling these bits violates IEEE 802.3 */
	TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
	TxCRC = (1 << 16),	/* DISABLE appending CRC to end of Tx packets */
	TxClearAbt = (1 << 0),	/* Clear abort (WO) */
	TxDMAShift = 8,		/* DMA burst value (0-7) is shift this many bits */

	TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
};

/* Bits in Config1 */
enum Config1Bits {
	Cfg1_PM_Enable = 0x01,
	Cfg1_VPD_Enable = 0x02,
	Cfg1_PIO = 0x04,
	Cfg1_MMIO = 0x08,
	LWAKE = 0x10,		/* not on 8139, 8139A */
	Cfg1_Driver_Load = 0x20,
	Cfg1_LED0 = 0x40,
	Cfg1_LED1 = 0x80,
	SLEEP = (1 << 1),	/* only on 8139, 8139A */
	PWRDN = (1 << 0),	/* only on 8139, 8139A */
};

/* Bits in Config4 */
enum Config4Bits {
	LWPTN = (1 << 2),	/* not on 8139, 8139A */
};

enum RxConfigBits {
	/* Early Rx threshold, none or X/16 */
	RxCfgEarlyRxNone = 0,
	RxCfgEarlyRxShift = 24,

	/* rx fifo threshold */
	RxCfgFIFOShift = 13,
	//no rx threshold. The RTL8139 begins the transfer of data after
	//having received a whole packet in the FIFO.
	RxCfgFIFONone = (7 << RxCfgFIFOShift), 

	/* Max DMA burst */
	RxCfgDMAShift = 8,
	RxCfgDMAUnlimited = (7 << RxCfgDMAShift), //unlimited

	/* rx ring buffer length */
	RxCfgRcv8K = 0,
	RxCfgRcv16K = (1 << 11),   //接收缓冲长度：16k + 16 byte
	RxCfgRcv32K = (1 << 12),
	RxCfgRcv64K = (1 << 11) | (1 << 12),

	RxNoWrap = (1 << 7),//The RTL8139D(L) will keep moving the rest of the
//packet data into the memory immediately after the end of the Rx buffer,
};
#define rtl8139_rx_config \
	  RxCfgEarlyRxNone | RxCfgRcv16K | RxNoWrap |(AcceptMyPhys | AcceptBroadcast | AcceptMulticast) | \
      (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift)	

/* Twister tuning parameters from RealTek.
   Completely undocumented, but required to tune bad links. */
enum CSCRBits {
	CSCR_LinkOKBit = 0x0400,
	CSCR_LinkChangeBit = 0x0800,
	CSCR_LinkStatusBits = 0x0f000,
	CSCR_LinkDownOffCmd = 0x003c0,
	CSCR_LinkDownCmd = 0x0f3c0,
};


enum Cfg9346Bits {
	Cfg9346_Lock = 0x00,
	Cfg9346_Unlock = 0xC0,
};

#define RX_FIFO_THRESH	2	/* Rx buffer level before first PCI xfer.  */
#define RX_DMA_BURST	4	/* Maximum PCI burst, '4' is 256 */
#define TX_DMA_BURST	4	/* Maximum PCI burst, '6' is 1024 */

#define RL_TXCFG_CONFIG	(TX_DMA_BURST << TxDMAShift)|TxIFG1|TxIFG0


/*
 * Under PCI, each device has 256 bytes of configuration address space,
 * of which the first 64 bytes are standardized as follows:
 */
#define PCI_VENDOR_ID		0x00	/* 16 bits */
#define PCI_DEVICE_ID		0x02	/* 16 bits */
#define PCI_COMMAND		0x04	/* 16 bits */
#define  PCI_COMMAND_IO		0x1	/* Enable response in I/O space */
#define  PCI_COMMAND_MEMORY	0x2	/* Enable response in Memory space */
#define  PCI_COMMAND_MASTER	0x4	/* Enable bus mastering */
#define  PCI_COMMAND_SPECIAL	0x8	/* Enable response to special cycles */
#define  PCI_COMMAND_INVALIDATE	0x10	/* Use memory write and invalidate */
#define  PCI_COMMAND_VGA_PALETTE 0x20	/* Enable palette snooping */
#define  PCI_COMMAND_PARITY	0x40	/* Enable parity checking */
#define  PCI_COMMAND_WAIT 	0x80	/* Enable address/data stepping */
#define  PCI_COMMAND_SERR	0x100	/* Enable SERR */
#define  PCI_COMMAND_FAST_BACK	0x200	/* Enable back-to-back writes */

#define PCI_STATUS		0x06	/* 16 bits */
#define  PCI_STATUS_CAP_LIST	0x10	/* Support Capability List */
#define  PCI_STATUS_66MHZ	0x20	/* Support 66 Mhz PCI 2.1 bus */
#define  PCI_STATUS_UDF		0x40	/* Support User Definable Features [obsolete] */
#define  PCI_STATUS_FAST_BACK	0x80	/* Accept fast-back to back */
#define  PCI_STATUS_PARITY	0x100	/* Detected parity error */
#define  PCI_STATUS_DEVSEL_MASK	0x600	/* DEVSEL timing */
#define  PCI_STATUS_DEVSEL_FAST	0x000	
#define  PCI_STATUS_DEVSEL_MEDIUM 0x200
#define  PCI_STATUS_DEVSEL_SLOW 0x400
#define  PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
#define  PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
#define  PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
#define  PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
#define  PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */

#define PCI_CLASS_REVISION	0x08	/* High 24 bits are class, low 8
					   revision */
#define PCI_REVISION_ID         0x08    /* Revision ID */
#define PCI_CLASS_PROG          0x09    /* Reg. Level Programming Interface */
#define PCI_CLASS_DEVICE        0x0a    /* Device class */

#define PCI_CACHE_LINE_SIZE	0x0c	/* 8 bits */
#define PCI_LATENCY_TIMER	0x0d	/* 8 bits */
#define PCI_HEADER_TYPE		0x0e	/* 8 bits */
#define  PCI_HEADER_TYPE_NORMAL	0
#define  PCI_HEADER_TYPE_BRIDGE 1
#define  PCI_HEADER_TYPE_CARDBUS 2

#define PCI_BIST		0x0f	/* 8 bits */
#define PCI_BIST_CODE_MASK	0x0f	/* Return result */
#define PCI_BIST_START		0x40	/* 1 to start BIST, 2 secs or less */
#define PCI_BIST_CAPABLE	0x80	/* 1 if BIST capable */

/*
 * Base addresses specify locations in memory or I/O space.
 * Decoded size can be determined by writing a value of 
 * 0xffffffff to the register, and reading it back.  Only 
 * 1 bits are decoded.
 */
#define PCI_BASE_ADDRESS_0	0x10	/* 32 bits */
#define PCI_BASE_ADDRESS_1	0x14	/* 32 bits [htype 0,1 only] */
#define PCI_BASE_ADDRESS_2	0x18	/* 32 bits [htype 0 only] */
#define PCI_BASE_ADDRESS_3	0x1c	/* 32 bits */
#define PCI_BASE_ADDRESS_4	0x20	/* 32 bits */
#define PCI_BASE_ADDRESS_5	0x24	/* 32 bits */