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📄 main.s90

📁 MMA7361加速度倾角模块
💻 S90
📖 第 1 页 / 共 3 页
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        MOV     R16, R25
        SUBI    R16, 208
        RCALL   SW_UART_Tx
        RJMP    ??Show_Hex_0
??Show_Hex_1:
        LDI     R30, 4
        JMP     ?EPILOGUE_B4_L09

        RSEG CODE:CODE:NOROOT(1)
// __nearfunc __version_3 void Put_Axis(unsigned int)
Put_Axis:
        CALL    ?PROLOGUE4_L09
        SBIW    R29:R28, 4
        MOVW    R25:R24, R17:R16
        LDI     R20, 232
        LDI     R21, 3
        MOVW    R17:R16, R25:R24
        CALL    ?US_DIVMOD_L02
        ST      Y, R16
        LDI     R20, 232
        LDI     R21, 3
        MOVW    R17:R16, R25:R24
        CALL    ?US_DIVMOD_L02
        MOVW    R17:R16, R21:R20
        LDI     R20, 100
        LDI     R21, 0
        CALL    ?US_DIVMOD_L02
        STD     Y+1, R16
        LDI     R20, 232
        LDI     R21, 3
        MOVW    R17:R16, R25:R24
        CALL    ?US_DIVMOD_L02
        MOVW    R17:R16, R21:R20
        LDI     R20, 100
        LDI     R21, 0
        CALL    ?US_DIVMOD_L02
        MOVW    R17:R16, R21:R20
        LDI     R20, 10
        LDI     R21, 0
        CALL    ?US_DIVMOD_L02
        STD     Y+2, R16
        LDI     R20, 232
        LDI     R21, 3
        MOVW    R17:R16, R25:R24
        CALL    ?US_DIVMOD_L02
        MOVW    R17:R16, R21:R20
        LDI     R20, 100
        LDI     R21, 0
        CALL    ?US_DIVMOD_L02
        MOVW    R17:R16, R21:R20
        LDI     R20, 10
        LDI     R21, 0
        CALL    ?US_DIVMOD_L02
        STD     Y+3, R20
        LDI     R26, 0
??Put_Axis_0:
        CPI     R26, 4
        BRCC    ??Put_Axis_1
        MOVW    R31:R30, R29:R28
        LDI     R27, 0
        ADD     R30, R26
        ADC     R31, R27
        LD      R16, Z
        SUBI    R16, 208
        RCALL   SW_UART_Tx
        INC     R26
        RJMP    ??Put_Axis_0
??Put_Axis_1:
        ADIW    R29:R28, 4
        LDI     R30, 4
        JMP     ?EPILOGUE_B4_L09

        RSEG CODE:CODE:NOROOT(1)
// __nearfunc __version_3 void UART_Init()
UART_Init:
        LDI     R16, 0
        STS     193, R16
        LDI     R16, 2
        STS     192, R16
        LDI     R16, 6
        STS     194, R16
        LDI     R16, 103
        STS     196, R16
        LDI     R16, 0
        STS     197, R16
        LDI     R16, 24
        STS     193, R16
        RET
        REQUIRE _A_UCSR0B
        REQUIRE _A_UCSR0A
        REQUIRE _A_UBRR0
        REQUIRE _A_UCSR0C

        RSEG CODE:CODE:NOROOT(1)
// __nearfunc __version_3 void UART_Tx(unsigned char)
UART_Tx:
??UART_Tx_0:
        LDS     R17, 192
        MOV     R18, R17
        SBRS    R18, 5
        RJMP    ??UART_Tx_0
        STS     198, R16
        RET
        REQUIRE _A_UDR0
        REQUIRE _A_UCSR0A

        RSEG CODE:CODE:NOROOT(1)
// __nearfunc __version_3 unsigned char UART_Rx()
UART_Rx:
??UART_Rx_0:
        LDS     R16, 192
        MOV     R17, R16
        SBRS    R17, 7
        RJMP    ??UART_Rx_0
        LDS     R16, 198
        RET
        REQUIRE _A_UDR0
        REQUIRE _A_UCSR0A
//   30 

        RSEG CODE:CODE:NOROOT(1)
//   31 int main(void)
main:
//   32 {
        ST      -Y, R25
        ST      -Y, R24
//   33   unsigned char i;
//   34   IO_Ports_Init();				//Initialize IO ports
        RCALL   IO_Ports_Init
//   35   Timers_Init();				//Initialize timers
        RCALL   Timers_Init
//   36   ADC_Init();					//Initialize ADC
        RCALL   ADC_Init
//   37   PRR = 0x82;                                   //Reduce consumption 86 (don't stop SPI)
        LDI     R16, 130
        STS     100, R16
//   38   CLKPR = 0x80;					//Increase Fcpu
        LDI     R16, 128
        STS     97, R16
//   39   CLKPR = 0x00;
        LDI     R16, 0
        STS     97, R16
//   40   TCCR2B = 0x06;
        LDI     R16, 6
        STS     177, R16
//   41 
//   42   __disable_interrupt();
        CLI
//   43   __watchdog_reset();
        WDR
//   44     WDTCSR = 0x18;				//Enable watchdog, timeout 256ms
        LDI     R16, 24
        STS     96, R16
//   45     WDTCSR = 0x0D;
        LDI     R16, 13
        STS     96, R16
//   46   __enable_interrupt();				//Enable interrupts
        SEI
//   47   
//   48   MMA7361_Init();
        RCALL   MMA7361_Init
//   49   while(1)
//   50   {
//   51     __watchdog_reset();				//Reset watchdog timer
??main_0:
        WDR
//   52       
//   53     if(ShowDebug_Cnt==0)							
        LDS     R16, ShowDebug_Cnt
        TST     R16
        BRNE    ??main_0
//   54     {
//   55     	ShowDebug_Cnt=30;//13;  				//Get data periodically
        LDI     R16, 30
        STS     ShowDebug_Cnt, R16
//   56     	for(i=0;i<Max_Axis;i++)					//Get Axis data 
        LDI     R24, 0
??main_1:
        CPI     R24, 3
        BRCC    ??main_2
//   57   			Axis_Data[i]=Get_ADC(i,10);
        LDI     R17, 10
        MOV     R16, R24
        RCALL   Get_ADC
        MOV     R18, R24
        LDI     R19, 0
        LSL     R18
        ROL     R19
        MOVW    R31:R30, R19:R18
        SUBI    R30, LOW((-(Axis_Data) & 0xFFFF))
        SBCI    R31, (-(Axis_Data) & 0xFFFF) >> 8
        ST      Z, R16
        STD     Z+1, R17
        INC     R24
        RJMP    ??main_1
//   58   		for(i=0;i<Max_Axis;i++)				//Show Axis data through UART
??main_2:
        LDI     R24, 0
??main_3:
        CPI     R24, 3
        BRCC    ??main_4
//   59   		{
//   60     		SW_UART_Tx(Axis_Name[i]);
        LDI     R25, 0
        MOVW    R31:R30, R25:R24
        SUBI    R30, LOW((-(Axis_Name) & 0xFFFF))
        SBCI    R31, (-(Axis_Name) & 0xFFFF) >> 8
        LD      R16, Z
        RCALL   SW_UART_Tx
//   61   			Put_Axis(Axis_Data[i]);
        MOV     R16, R24
        LDI     R17, 0
        LSL     R16
        ROL     R17
        MOVW    R31:R30, R17:R16
        SUBI    R30, LOW((-(Axis_Data) & 0xFFFF))
        SBCI    R31, (-(Axis_Data) & 0xFFFF) >> 8
        LD      R16, Z
        LDD     R17, Z+1
        RCALL   Put_Axis
//   62     		SW_UART_Tx(' ');
        LDI     R16, 32
        RCALL   SW_UART_Tx
//   63   		}
        INC     R24
        RJMP    ??main_3
//   64     	SW_UART_Tx(' ');					//Next Line
??main_4:
        LDI     R16, 32
        RCALL   SW_UART_Tx
//   65     	SW_UART_Tx(0x0d);
        LDI     R16, 13
        RCALL   SW_UART_Tx
        RJMP    ??main_0
        REQUIRE _A_TCCR2B
        REQUIRE _A_PRR
        REQUIRE _A_CLKPR
        REQUIRE _A_WDTCSR
//   66   	}
//   67   }
//   68   
//   69   
//   70 }
//   71 
//   72 //SIGNAL(SIG_OVERFLOW2)
//   73 #pragma vector=TIMER2_OVF_vect
//   74 

        RSEG CODE:CODE:NOROOT(1)
//   75 __interrupt void TMR2irq( void )
TMR2irq:
//   76 
//   77 {
        ST      -Y, R31
        ST      -Y, R30
        ST      -Y, R17
        ST      -Y, R16
        IN      R17, 0x3F
//   78   if(ShowDebug_Cnt!=0)
        LDS     R16, ShowDebug_Cnt
        TST     R16
        BREQ    ??TMR2irq_0
//   79   	ShowDebug_Cnt--;
        LDI     R30, LOW(ShowDebug_Cnt)
        LDI     R31, (ShowDebug_Cnt) >> 8
        LD      R16, Z
        DEC     R16
        ST      Z, R16
//   80 }
??TMR2irq_0:
        OUT     0x3F, R17
        LD      R16, Y+
        LD      R17, Y+
        LD      R30, Y+
        LD      R31, Y+
        RETI
//   81 
//   82 //SIGNAL(SIG_ADC)
//   83 #pragma vector=ADC_vect
//   84 

        RSEG CODE:CODE:NOROOT(1)
//   85 __interrupt void ADCirq( void )
ADCirq:
//   86 {
        ST      -Y, R31
        ST      -Y, R30
        ST      -Y, R0
        ST      -Y, R23
        ST      -Y, R22
        ST      -Y, R21
        ST      -Y, R20
        ST      -Y, R19
        ST      -Y, R18
        ST      -Y, R17
        ST      -Y, R16
        IN      R0, 0x3F
//   87   SumReg += ADC; 								//Add result to common sum
        LDS     R16, 120
        LDS     R17, 121
        LDI     R18, 0
        LDI     R19, 0
        LDI     R30, LOW(SumReg)
        LDI     R31, (SumReg) >> 8
        LD      R20, Z
        LDD     R21, Z+1
        LDD     R22, Z+2
        LDD     R23, Z+3
        ADD     R20, R16
        ADC     R21, R17
        ADC     R22, R18
        ADC     R23, R19
        ST      Z, R20
        STD     Z+1, R21
        STD     Z+2, R22
        STD     Z+3, R23
//   88   if(--SampCnt == 0)								//Check number of samples
        LDS     R16, SampCnt
        DEC     R16
        STS     SampCnt, R16
        TST     R16
        BRNE    ??ADCirq_0
//   89   {
//   90 	ADC_Done=1;								//Measuring is complete
        LDI     R16, 1
        STS     ADC_Done, R16
//   91 	ADCSRA = 0x80;							        //Stop ADC
        LDI     R16, 128
        STS     122, R16
        RJMP    ??ADCirq_1
//   92   }
//   93   else
//   94   {
//   95 	ADCSRA |= 0x40;								//Start next ADC cycle
??ADCirq_0:
        LDS     R16, 122
        ORI     R16, 0x40
        STS     122, R16
//   96   }
//   97 }
??ADCirq_1:
        OUT     0x3F, R0
        LD      R16, Y+
        LD      R17, Y+
        LD      R18, Y+
        LD      R19, Y+
        LD      R20, Y+
        LD      R21, Y+
        LD      R22, Y+
        LD      R23, Y+
        LD      R0, Y+
        LD      R30, Y+
        LD      R31, Y+
        RETI
        REQUIRE _A_ADCSRA
        REQUIRE _A_ADC

        ASEGN ABSOLUTE:DATA:NOROOT,01fH
__?EECR:

        ASEGN ABSOLUTE:DATA:NOROOT,020H
__?EEDR:

        ASEGN ABSOLUTE:DATA:NOROOT,021H
__?EEARL:

        ASEGN ABSOLUTE:DATA:NOROOT,022H
__?EEARH:

        COMMON INTVEC:CODE:ROOT(1)
        ORG 36
`??TMR2irq??INTVEC 36`:
        JMP     TMR2irq

        COMMON INTVEC:CODE:ROOT(1)
        ORG 84
`??ADCirq??INTVEC 84`:
        JMP     ADCirq

        RSEG NEAR_ID:CODE:ROOT(0)
`?<Initializer for Channel_Tbl>`:
        DB 66, 65, 64

        RSEG INITTAB:CODE:NOROOT(0)
`?<Segment init: NEAR_I>`:
        DW      SFE(NEAR_I) - SFB(NEAR_I)
        DW      SFB(NEAR_I)
        DW      SFB(NEAR_ID)
        REQUIRE ?need_segment_init

        RSEG NEAR_ID:CODE:ROOT(0)
`?<Initializer for Axis_Name>`:
        DB 88, 89, 90

        RSEG INITTAB:CODE:NOROOT(0)
`?<Segment init: NEAR_Z>`:
        DW      SFE(NEAR_Z) - SFB(NEAR_Z)
        DW      SFB(NEAR_Z)
        DW      0
        REQUIRE ?need_segment_init

        END
//   98 
//   99 //SIGNAL(__vector_default)
//  100 //#pragma vector=default
//  101 
// 
//  87 bytes in segment ABSOLUTE
// 910 bytes in segment CODE
//  12 bytes in segment INITTAB
//   8 bytes in segment INTVEC
//   6 bytes in segment NEAR_I
//   6 bytes in segment NEAR_ID
//  15 bytes in segment NEAR_Z
// 
// 916 bytes of CODE memory (+ 20 bytes shared)
//  21 bytes of DATA memory (+ 87 bytes shared)
//
//Errors: none
//Warnings: none

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