📄 main.s90
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///////////////////////////////////////////////////////////////////////////////
// /
// 09/May/2011 01:08:12 /
// IAR Atmel AVR C/C++ Compiler V5.11B/W32, Evaluation Version /
// Copyright 1996-2008 IAR Systems. All rights reserved. /
// /
// Source file = F:\Lcsoft\Hardware\AVR\MMA7361\main.c /
// Command line = F:\Lcsoft\Hardware\AVR\MMA7361\main.c --cpu=m168 -ms /
// -o F:\Lcsoft\Hardware\AVR\MMA7361\Debug\Obj\ -lCN /
// F:\Lcsoft\Hardware\AVR\MMA7361\Debug\List\ -lB /
// F:\Lcsoft\Hardware\AVR\MMA7361\Debug\List\ /
// --initializers_in_flash --root_variables -z2 --no_cse /
// --no_inline --no_code_motion --no_cross_call /
// --no_clustering --no_tbaa --debug -I "C:\Program Files /
// (x86)\IAR Systems\Embedded Workbench 5.0 /
// Evaluation\avr\INC\" -I "C:\Program Files (x86)\IAR /
// Systems\Embedded Workbench 5.0 /
// Evaluation\avr\INC\CLIB\" --eeprom_size 512 /
// List file = F:\Lcsoft\Hardware\AVR\MMA7361\Debug\List\main.s90 /
// /
// /
///////////////////////////////////////////////////////////////////////////////
NAME main
RSEG CSTACK:DATA:NOROOT(0)
RSEG RSTACK:DATA:NOROOT(0)
EXTERN ?EPILOGUE_B4_L09
EXTERN ?EPILOGUE_B5_L09
EXTERN ?PROLOGUE4_L09
EXTERN ?PROLOGUE5_L09
EXTERN ?Register_R4_is_cg_reg
EXTERN ?UL_DIVMOD_L03
EXTERN ?US_DIVMOD_L02
EXTERN ?US_SHR_L02
EXTERN ?need_segment_init
PUBWEAK `?<Segment init: NEAR_I>`
PUBWEAK `?<Segment init: NEAR_Z>`
PUBWEAK `??ADCirq??INTVEC 84`
PUBWEAK `??TMR2irq??INTVEC 36`
PUBLIC ADC_Done
PUBLIC ADC_Init
PUBLIC ADCirq
PUBLIC Axis_Data
PUBLIC Axis_Name
PUBLIC Channel_Tbl
PUBLIC Get_ADC
PUBLIC IO_Ports_Init
PUBLIC MMA7361_Init
PUBLIC Put_Axis
PUBLIC SW_UART_Tx
PUBLIC ShowDebug_Cnt
PUBLIC Show_Hex
PUBLIC SumReg
PUBLIC TMR2irq
PUBLIC Temp
PUBLIC Temp1
PUBLIC Timers_Init
PUBLIC UART_Init
PUBLIC UART_Rx
PUBLIC UART_Tx
PUBWEAK _A_ACSR
PUBWEAK _A_ADC
PUBWEAK _A_ADCSRA
PUBWEAK _A_ADCSRB
PUBWEAK _A_ADMUX
PUBWEAK _A_ASSR
PUBWEAK _A_CLKPR
PUBWEAK _A_DDRB
PUBWEAK _A_DDRC
PUBWEAK _A_DDRD
PUBWEAK _A_DIDR0
PUBWEAK _A_DIDR1
PUBWEAK _A_EEAR
PUBWEAK _A_EECR
PUBWEAK _A_EEDR
PUBWEAK _A_EICRA
PUBWEAK _A_EIFR
PUBWEAK _A_EIMSK
PUBWEAK _A_GPIOR0
PUBWEAK _A_GPIOR1
PUBWEAK _A_GPIOR2
PUBWEAK _A_GTCCR
PUBWEAK _A_ICR1
PUBWEAK _A_MCUCR
PUBWEAK _A_MCUSR
PUBWEAK _A_OCR0A
PUBWEAK _A_OCR0B
PUBWEAK _A_OCR1A
PUBWEAK _A_OCR1B
PUBWEAK _A_OCR2A
PUBWEAK _A_OCR2B
PUBWEAK _A_OSCCAL
PUBWEAK _A_PCICR
PUBWEAK _A_PCIFR
PUBWEAK _A_PCMSK0
PUBWEAK _A_PCMSK1
PUBWEAK _A_PCMSK2
PUBWEAK _A_PINB
PUBWEAK _A_PINC
PUBWEAK _A_PIND
PUBWEAK _A_PORTB
PUBWEAK _A_PORTC
PUBWEAK _A_PORTD
PUBWEAK _A_PRR
PUBWEAK _A_SMCR
PUBWEAK _A_SP
PUBWEAK _A_SPCR
PUBWEAK _A_SPDR
PUBWEAK _A_SPMCSR
PUBWEAK _A_SPSR
PUBWEAK _A_SREG
PUBWEAK _A_TCCR0A
PUBWEAK _A_TCCR0B
PUBWEAK _A_TCCR1A
PUBWEAK _A_TCCR1B
PUBWEAK _A_TCCR1C
PUBWEAK _A_TCCR2A
PUBWEAK _A_TCCR2B
PUBWEAK _A_TCNT0
PUBWEAK _A_TCNT1
PUBWEAK _A_TCNT2
PUBWEAK _A_TIFR0
PUBWEAK _A_TIFR1
PUBWEAK _A_TIFR2
PUBWEAK _A_TIMSK0
PUBWEAK _A_TIMSK1
PUBWEAK _A_TIMSK2
PUBWEAK _A_TWAMR
PUBWEAK _A_TWAR
PUBWEAK _A_TWBR
PUBWEAK _A_TWCR
PUBWEAK _A_TWDR
PUBWEAK _A_TWSR
PUBWEAK _A_UBRR0
PUBWEAK _A_UCSR0A
PUBWEAK _A_UCSR0B
PUBWEAK _A_UCSR0C
PUBWEAK _A_UDR0
PUBWEAK _A_WDTCSR
PUBWEAK __?EEARH
PUBWEAK __?EEARL
PUBWEAK __?EECR
PUBWEAK __?EEDR
PUBLIC main
ADCirq SYMBOL "ADCirq"
`??ADCirq??INTVEC 84` SYMBOL "??INTVEC 84", ADCirq
TMR2irq SYMBOL "TMR2irq"
`??TMR2irq??INTVEC 36` SYMBOL "??INTVEC 36", TMR2irq
// F:\Lcsoft\Hardware\AVR\MMA7361\main.c
// 1 //-------------------------------------------------------------------
// 2 // MMA7361 Demo code, show the 3 axis date through UART periodically
// 3 // Hardware connection: X_out PC2
// 4 // Y_out PC1
// 5 // Z_out PC0
// 6 // MMA7361_En PC3
// 7 // UART_Tx PD1
// 8 // Software UART baudrate 115200 when main frequency is 4M
// 9 //-------------------------------------------------------------------
// 10
// 11 #include "iom168.h"
ASEGN ABSOLUTE:DATA:ROOT,0c6H
// <unnamed> volatile __io _A_UDR0
_A_UDR0:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0c4H
// <unnamed> volatile __io _A_UBRR0
_A_UBRR0:
DS 2
ASEGN ABSOLUTE:DATA:ROOT,0c2H
// <unnamed> volatile __io _A_UCSR0C
_A_UCSR0C:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0c1H
// <unnamed> volatile __io _A_UCSR0B
_A_UCSR0B:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0c0H
// <unnamed> volatile __io _A_UCSR0A
_A_UCSR0A:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0bdH
// <unnamed> volatile __io _A_TWAMR
_A_TWAMR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0bcH
// <unnamed> volatile __io _A_TWCR
_A_TWCR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0bbH
// <unnamed> volatile __io _A_TWDR
_A_TWDR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0baH
// <unnamed> volatile __io _A_TWAR
_A_TWAR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0b9H
// <unnamed> volatile __io _A_TWSR
_A_TWSR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0b8H
// <unnamed> volatile __io _A_TWBR
_A_TWBR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0b6H
// <unnamed> volatile __io _A_ASSR
_A_ASSR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0b4H
// <unnamed> volatile __io _A_OCR2B
_A_OCR2B:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0b3H
// <unnamed> volatile __io _A_OCR2A
_A_OCR2A:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0b2H
// <unnamed> volatile __io _A_TCNT2
_A_TCNT2:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0b1H
// <unnamed> volatile __io _A_TCCR2B
_A_TCCR2B:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,0b0H
// <unnamed> volatile __io _A_TCCR2A
_A_TCCR2A:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,08aH
// <unnamed> volatile __io _A_OCR1B
_A_OCR1B:
DS 2
ASEGN ABSOLUTE:DATA:ROOT,088H
// <unnamed> volatile __io _A_OCR1A
_A_OCR1A:
DS 2
ASEGN ABSOLUTE:DATA:ROOT,086H
// <unnamed> volatile __io _A_ICR1
_A_ICR1:
DS 2
ASEGN ABSOLUTE:DATA:ROOT,084H
// <unnamed> volatile __io _A_TCNT1
_A_TCNT1:
DS 2
ASEGN ABSOLUTE:DATA:ROOT,082H
// <unnamed> volatile __io _A_TCCR1C
_A_TCCR1C:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,081H
// <unnamed> volatile __io _A_TCCR1B
_A_TCCR1B:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,080H
// <unnamed> volatile __io _A_TCCR1A
_A_TCCR1A:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,07fH
// <unnamed> volatile __io _A_DIDR1
_A_DIDR1:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,07eH
// <unnamed> volatile __io _A_DIDR0
_A_DIDR0:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,07cH
// <unnamed> volatile __io _A_ADMUX
_A_ADMUX:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,07bH
// <unnamed> volatile __io _A_ADCSRB
_A_ADCSRB:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,07aH
// <unnamed> volatile __io _A_ADCSRA
_A_ADCSRA:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,078H
// <unnamed> volatile __io _A_ADC
_A_ADC:
DS 2
ASEGN ABSOLUTE:DATA:ROOT,070H
// <unnamed> volatile __io _A_TIMSK2
_A_TIMSK2:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,06fH
// <unnamed> volatile __io _A_TIMSK1
_A_TIMSK1:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,06eH
// <unnamed> volatile __io _A_TIMSK0
_A_TIMSK0:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,06dH
// <unnamed> volatile __io _A_PCMSK2
_A_PCMSK2:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,06cH
// <unnamed> volatile __io _A_PCMSK1
_A_PCMSK1:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,06bH
// <unnamed> volatile __io _A_PCMSK0
_A_PCMSK0:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,069H
// <unnamed> volatile __io _A_EICRA
_A_EICRA:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,068H
// <unnamed> volatile __io _A_PCICR
_A_PCICR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,066H
// <unnamed> volatile __io _A_OSCCAL
_A_OSCCAL:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,064H
// <unnamed> volatile __io _A_PRR
_A_PRR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,061H
// <unnamed> volatile __io _A_CLKPR
_A_CLKPR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,060H
// <unnamed> volatile __io _A_WDTCSR
_A_WDTCSR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,05fH
// <unnamed> volatile __io _A_SREG
_A_SREG:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,05dH
// <unnamed> volatile __io _A_SP
_A_SP:
DS 2
ASEGN ABSOLUTE:DATA:ROOT,057H
// <unnamed> volatile __io _A_SPMCSR
_A_SPMCSR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,055H
// <unnamed> volatile __io _A_MCUCR
_A_MCUCR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,054H
// <unnamed> volatile __io _A_MCUSR
_A_MCUSR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,053H
// <unnamed> volatile __io _A_SMCR
_A_SMCR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,050H
// <unnamed> volatile __io _A_ACSR
_A_ACSR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,04eH
// <unnamed> volatile __io _A_SPDR
_A_SPDR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,04dH
// <unnamed> volatile __io _A_SPSR
_A_SPSR:
DS 1
ASEGN ABSOLUTE:DATA:ROOT,04cH
// <unnamed> volatile __io _A_SPCR
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