📄 main.lst
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###############################################################################
# #
# 09/May/2011 01:08:12 #
# IAR Atmel AVR C/C++ Compiler V5.11B/W32, Evaluation Version #
# Copyright 1996-2008 IAR Systems. All rights reserved. #
# #
# Source file = F:\Lcsoft\Hardware\AVR\MMA7361\main.c #
# Command line = F:\Lcsoft\Hardware\AVR\MMA7361\main.c --cpu=m168 -ms -o #
# F:\Lcsoft\Hardware\AVR\MMA7361\Debug\Obj\ -lCN #
# F:\Lcsoft\Hardware\AVR\MMA7361\Debug\List\ -lB #
# F:\Lcsoft\Hardware\AVR\MMA7361\Debug\List\ #
# --initializers_in_flash --root_variables -z2 --no_cse #
# --no_inline --no_code_motion --no_cross_call #
# --no_clustering --no_tbaa --debug -I "C:\Program Files #
# (x86)\IAR Systems\Embedded Workbench 5.0 #
# Evaluation\avr\INC\" -I "C:\Program Files (x86)\IAR #
# Systems\Embedded Workbench 5.0 #
# Evaluation\avr\INC\CLIB\" --eeprom_size 512 #
# List file = F:\Lcsoft\Hardware\AVR\MMA7361\Debug\List\main.lst #
# Object file = F:\Lcsoft\Hardware\AVR\MMA7361\Debug\Obj\main.r90 #
# #
# #
###############################################################################
F:\Lcsoft\Hardware\AVR\MMA7361\main.c
1 //-------------------------------------------------------------------
2 // MMA7361 Demo code, show the 3 axis date through UART periodically
3 // Hardware connection: X_out PC2
4 // Y_out PC1
5 // Z_out PC0
6 // MMA7361_En PC3
7 // UART_Tx PD1
8 // Software UART baudrate 115200 when main frequency is 4M
9 //-------------------------------------------------------------------
10
11 #include "iom168.h"
\ In segment ABSOLUTE, at 0xc6, root
\ <unnamed> volatile __io _A_UDR0
\ _A_UDR0:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xc4, root
\ <unnamed> volatile __io _A_UBRR0
\ _A_UBRR0:
\ 00000000 DS 2
\ In segment ABSOLUTE, at 0xc2, root
\ <unnamed> volatile __io _A_UCSR0C
\ _A_UCSR0C:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xc1, root
\ <unnamed> volatile __io _A_UCSR0B
\ _A_UCSR0B:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xc0, root
\ <unnamed> volatile __io _A_UCSR0A
\ _A_UCSR0A:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xbd, root
\ <unnamed> volatile __io _A_TWAMR
\ _A_TWAMR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xbc, root
\ <unnamed> volatile __io _A_TWCR
\ _A_TWCR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xbb, root
\ <unnamed> volatile __io _A_TWDR
\ _A_TWDR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xba, root
\ <unnamed> volatile __io _A_TWAR
\ _A_TWAR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xb9, root
\ <unnamed> volatile __io _A_TWSR
\ _A_TWSR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xb8, root
\ <unnamed> volatile __io _A_TWBR
\ _A_TWBR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xb6, root
\ <unnamed> volatile __io _A_ASSR
\ _A_ASSR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xb4, root
\ <unnamed> volatile __io _A_OCR2B
\ _A_OCR2B:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xb3, root
\ <unnamed> volatile __io _A_OCR2A
\ _A_OCR2A:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xb2, root
\ <unnamed> volatile __io _A_TCNT2
\ _A_TCNT2:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xb1, root
\ <unnamed> volatile __io _A_TCCR2B
\ _A_TCCR2B:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0xb0, root
\ <unnamed> volatile __io _A_TCCR2A
\ _A_TCCR2A:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x8a, root
\ <unnamed> volatile __io _A_OCR1B
\ _A_OCR1B:
\ 00000000 DS 2
\ In segment ABSOLUTE, at 0x88, root
\ <unnamed> volatile __io _A_OCR1A
\ _A_OCR1A:
\ 00000000 DS 2
\ In segment ABSOLUTE, at 0x86, root
\ <unnamed> volatile __io _A_ICR1
\ _A_ICR1:
\ 00000000 DS 2
\ In segment ABSOLUTE, at 0x84, root
\ <unnamed> volatile __io _A_TCNT1
\ _A_TCNT1:
\ 00000000 DS 2
\ In segment ABSOLUTE, at 0x82, root
\ <unnamed> volatile __io _A_TCCR1C
\ _A_TCCR1C:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x81, root
\ <unnamed> volatile __io _A_TCCR1B
\ _A_TCCR1B:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x80, root
\ <unnamed> volatile __io _A_TCCR1A
\ _A_TCCR1A:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x7f, root
\ <unnamed> volatile __io _A_DIDR1
\ _A_DIDR1:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x7e, root
\ <unnamed> volatile __io _A_DIDR0
\ _A_DIDR0:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x7c, root
\ <unnamed> volatile __io _A_ADMUX
\ _A_ADMUX:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x7b, root
\ <unnamed> volatile __io _A_ADCSRB
\ _A_ADCSRB:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x7a, root
\ <unnamed> volatile __io _A_ADCSRA
\ _A_ADCSRA:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x78, root
\ <unnamed> volatile __io _A_ADC
\ _A_ADC:
\ 00000000 DS 2
\ In segment ABSOLUTE, at 0x70, root
\ <unnamed> volatile __io _A_TIMSK2
\ _A_TIMSK2:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x6f, root
\ <unnamed> volatile __io _A_TIMSK1
\ _A_TIMSK1:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x6e, root
\ <unnamed> volatile __io _A_TIMSK0
\ _A_TIMSK0:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x6d, root
\ <unnamed> volatile __io _A_PCMSK2
\ _A_PCMSK2:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x6c, root
\ <unnamed> volatile __io _A_PCMSK1
\ _A_PCMSK1:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x6b, root
\ <unnamed> volatile __io _A_PCMSK0
\ _A_PCMSK0:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x69, root
\ <unnamed> volatile __io _A_EICRA
\ _A_EICRA:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x68, root
\ <unnamed> volatile __io _A_PCICR
\ _A_PCICR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x66, root
\ <unnamed> volatile __io _A_OSCCAL
\ _A_OSCCAL:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x64, root
\ <unnamed> volatile __io _A_PRR
\ _A_PRR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x61, root
\ <unnamed> volatile __io _A_CLKPR
\ _A_CLKPR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x60, root
\ <unnamed> volatile __io _A_WDTCSR
\ _A_WDTCSR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x5f, root
\ <unnamed> volatile __io _A_SREG
\ _A_SREG:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x5d, root
\ <unnamed> volatile __io _A_SP
\ _A_SP:
\ 00000000 DS 2
\ In segment ABSOLUTE, at 0x57, root
\ <unnamed> volatile __io _A_SPMCSR
\ _A_SPMCSR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x55, root
\ <unnamed> volatile __io _A_MCUCR
\ _A_MCUCR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x54, root
\ <unnamed> volatile __io _A_MCUSR
\ _A_MCUSR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x53, root
\ <unnamed> volatile __io _A_SMCR
\ _A_SMCR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x50, root
\ <unnamed> volatile __io _A_ACSR
\ _A_ACSR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x4e, root
\ <unnamed> volatile __io _A_SPDR
\ _A_SPDR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x4d, root
\ <unnamed> volatile __io _A_SPSR
\ _A_SPSR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x4c, root
\ <unnamed> volatile __io _A_SPCR
\ _A_SPCR:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x4b, root
\ <unnamed> volatile __io _A_GPIOR2
\ _A_GPIOR2:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x4a, root
\ <unnamed> volatile __io _A_GPIOR1
\ _A_GPIOR1:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x48, root
\ <unnamed> volatile __io _A_OCR0B
\ _A_OCR0B:
\ 00000000 DS 1
\ In segment ABSOLUTE, at 0x47, root
\ <unnamed> volatile __io _A_OCR0A
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